Rename implicit clock/reset to referenceclock/reset

2023-05-12 15:11:44 -07:00
parent 94d471bd9a
commit b8e95e0305
7 changed files with 20 additions and 20 deletions
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -76,8 +76,8 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell

    harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)

-    def implicitClock = dutClock.in.head._1.clock
-    def implicitReset = dutClock.in.head._1.reset
+    def referenceClock = dutClock.in.head._1.clock
+    def referenceReset = dutClock.in.head._1.reset
    def success = { require(false, "Unused"); false.B }

    ddrOverlay.mig.module.clock := harnessBinderClock