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Update Idealized PLL config

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This commit is contained in:
David Biancolin
2020-09-16 16:30:25 -07:00
parent 8e4dedcecf
commit b8d3e4a66d
2 changed files with 3 additions and 3 deletions
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4
generators/chipyard/src/main/scala/Clocks.scala
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@@ -179,7 +179,7 @@ object ClockingSchemeGenerators {
implicit val p = chiptop.p implicit val p = chiptop.p
// Requires existence of undriven asyncClockGroups in subsystem // Requires existence of undriven asyncClockGroups in subsystem
val systemAsyncClockGroup = chiptop.lSystem match { val systemAsyncClockGroup = chiptop.lazySystem match {
case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) =>
l.asyncClockGroupsNode l.asyncClockGroupsNode
} }
@@ -204,7 +204,7 @@ object ClockingSchemeGenerators {
o.reset := reset_wire o.reset := reset_wire
} }
chiptop.harnessFunctions += ((th: HasHarnessUtils) => { chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
clock_io := th.harnessClock clock_io := th.harnessClock
Nil }) Nil })
} }

2
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -193,5 +193,5 @@ class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => {
}) })
class WithIdealizedPLL extends Config((site, here, up) => { class WithIdealizedPLL extends Config((site, here, up) => {
case ChipyardClockKey => ClockDrivers.idealizedPLL case ClockingSchemeKey => ClockingSchemeGenerators.idealizedPLL
}) })