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Add comments on ResetStretchers

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This commit is contained in:
Jerry Zhao
2023-04-08 14:54:25 -07:00
parent b7b2a62d80
commit b88e1025e4
2 changed files with 3 additions and 0 deletions
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2
generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
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@@ -41,6 +41,8 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
// Note this is not synchronized to the output clock, which takes time to appear // Note this is not synchronized to the output clock, which takes time to appear
// so this is still asyncreset // so this is still asyncreset
// Stretch the reset for 40 cycles, to give enough time to reset any downstream
// digital logic
sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
reg reg
} }

1
generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
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@@ -59,6 +59,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
mux.io.sel := sel mux.io.sel := sel
mux.io.resetAsync := asyncReset.asAsyncReset mux.io.resetAsync := asyncReset.asAsyncReset
sinks(i).clock := mux.io.clockOut sinks(i).clock := mux.io.clockOut
// Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
reg reg