From b7bc9895cbf2ec8746aca030ed2704ab8e5021a6 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 27 Feb 2024 23:53:36 -0800
Subject: [PATCH] Add old TLSerdes

---
 generators/chipyard/src/main/scala/DigitalTop.scala | 3 ++-
 generators/testchipip                               | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index bd82585b..ae0c8dad 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -19,7 +19,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
   with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
+  with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
   with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
   with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
   with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
diff --git a/generators/testchipip b/generators/testchipip
index be9c416d..5d6ec23c 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit be9c416d6a64462a28433a3eee808cf6cfacdd25
+Subproject commit 5d6ec23cd6d60299615700c00021fc5f69f57788