wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

rename missing vcs/verilator names | fix ci path

Browse Source
This commit is contained in:
abejgonzalez
2019-07-16 21:36:36 -07:00
parent 52f959f457
commit b7bc96b6d6
8 changed files with 14 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
docs/Getting-Started/Running-A-Simulation.rst
View File

@@ -15,9 +15,9 @@ The following instructions assume at least one of these simulators is installed.
Verilator/VCS Flows
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Verilator is an open-source RTL simulator.
We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
We run Verilator simulations from within the ``sims/verilator`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
On the other hand, VCS is a proprietary RTL simulator.
We run VCS simulations from within the ``sims/vsim`` directory.
We run VCS simulations from within the ``sims/vcs`` directory.
Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS.
First, we will start by entering the Verilator or VCS directory:
@@ -25,12 +25,12 @@ First, we will start by entering the Verilator or VCS directory:
.. code-block:: shell
# Enter Verilator directory
cd sims/verisim
cd sims/verilator
# OR
# Enter VCS directory
cd sims/vsim
cd sims/vcs
In order to construct the simulator with our custom design, we run the following command within the simulator directory: