Add RANDOM_SEED variable to set random init for VCS and Verilator simulations

2020-07-16 18:30:05 -07:00
parent 862d1fb774
commit b719919934
5 changed files with 24 additions and 11 deletions
--- a/vcs.mk
+++ b/vcs.mk
@@ -1,5 +1,13 @@
 WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd

+# If ntb_random_seed unspecified, vcs uses 1 as constant seed.
+# Set ntb_random_seed_automatic to actually get a random seed
+ifdef RANDOM_SEED
+SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
+else
+SEED_FLAG=+ntb_random_seed_automatic
+endif
+
 CLOCK_PERIOD ?= 1.0
 RESET_DELAY ?= 777.7