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Add RANDOM_SEED variable to set random init for VCS and Verilator simulations

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This commit is contained in:
Jerry Zhao
2020-07-16 18:30:05 -07:00
parent 862d1fb774
commit b719919934
5 changed files with 24 additions and 11 deletions
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6
sims/vcs/Makefile
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@@ -47,13 +47,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(E
# vcs simulator rules
#########################################################################################
$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-debug_pp
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@
$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+define+DEBUG \
-debug_pp
+define+DEBUG
#########################################################################################
# create a vcs vpd rule