Merge remote-tracking branch 'origin/main' into unify

.github/scripts/run-tests.sh

@@ -110,7 +110,8 @@ case $1 in
         make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
         ;;
     chipyard-ibex)
-        run_bmark ${mapping[$1]} #TODO: Find 32-bit test
+        # Ibex cannot run the riscv-tests binaries for some reason
+        # make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple
         ;;
     chipyard-sodor)
         run_asm ${mapping[$1]}

.gitmodules

@@ -121,3 +121,6 @@
 [submodule "tools/cde"]
 	path = tools/cde
 	url = https://github.com/chipsalliance/cde.git
+[submodule "software/embench/embench-iot"]
+	path = software/embench/embench-iot
+	url = https://github.com/embench/embench-iot.git

common.mk

@@ -292,6 +292,11 @@ check-binary:
 ifeq (,$(BINARY))
 	$(error BINARY variable is not set. Set it to the simulation binary)
 endif
+ifneq (none,$(BINARY))
+ifeq ("$(wildcard $(BINARY))","")
+	$(error BINARY=$(BINARY) not found)
+endif
+endif
 
 # allow you to override sim prereq
 ifeq (,$(BREAK_SIM_PREREQ))
@@ -309,6 +314,9 @@ run-binary-fast: $(SIM_PREREQ) check-binary | $(output_dir)
 
 # run simulator with as much debug info as possible
 run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir)
+ifneq (none,$(BINARY))
+	riscv64-unknown-elf-objdump -D $(BINARY) > $(sim_out_name).dump
+endif
 	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
 
 run-fast: run-asm-tests-fast run-bmark-tests-fast

generators/chipyard/src/main/resources/csrc/cospike.cc

@@ -63,7 +63,8 @@ extern "C" void cospike_set_sysinfo(char* isa, int pmpregions,
                                     ) {
   if (!info) {
     info = new system_info_t;
-    info->isa = std::string(isa);
+    // technically the targets aren't zicntr compliant, but they implement the zicntr registers
+    info->isa = std::string(isa) + "_zicntr";
     info->pmpregions = pmpregions;
     info->mem0_base = mem0_base;
     info->mem0_size = mem0_size;
@@ -266,12 +267,15 @@ extern "C" void cospike_cosim(long long int cycle,
 #endif
   uint64_t s_pc = s->pc;
   uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF;
+  bool ssip_interrupt = interrupt_cause == 0x1;
   bool msip_interrupt = interrupt_cause == 0x3;
   bool debug_interrupt = interrupt_cause == 0xe;
   if (raise_interrupt) {
     printf("%d interrupt %lx\n", cycle, cause);
 
-    if (msip_interrupt) {
+    if (ssip_interrupt) {
+      // do nothing
+    } else if (msip_interrupt) {
       s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP);
     } else if (debug_interrupt) {
       return;
@@ -285,9 +289,9 @@ extern "C" void cospike_cosim(long long int cycle,
   if (valid) {
     p->clear_waiting_for_interrupt();
     printf("%d Cosim: %lx", cycle, iaddr);
-    if (has_wdata) {
+    // if (has_wdata) {
-      printf(" s: %lx", wdata);
+    //   printf(" s: %lx", wdata);
-    }
+    // }
     printf("\n");
   }
   if (valid || raise_interrupt || raise_exception) {
@@ -301,7 +305,7 @@ extern "C" void cospike_cosim(long long int cycle,
     }
   }
 
-  if (valid) {
+  if (valid && !raise_exception) {
     if (s_pc != iaddr) {
       printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr);
       if (unlikely(cospike_debug)) {
@@ -375,12 +379,13 @@ extern "C" void cospike_cosim(long long int cycle,
         bool csr_read = (insn & 0x7f) == 0x73;
         if (csr_read)
           printf("CSR read %lx\n", csr_addr);
-        if (csr_read && ((csr_addr == 0xf13) ||                   // mimpid
+        if (csr_read && ((csr_addr == 0xf13) ||                      // mimpid
-                         (csr_addr == 0xf12) ||                   // marchid
+                         (csr_addr == 0xf12) ||                      // marchid
-                         (csr_addr == 0xf11) ||                   // mvendorid
+                         (csr_addr == 0xf11) ||                      // mvendorid
-                         (csr_addr == 0xb00) ||                   // mcycle
+                         (csr_addr == 0xb00) ||                      // mcycle
-                         (csr_addr == 0xb02) ||                   // minstret
+                         (csr_addr == 0xb02) ||                      // minstret
-                         (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr
+                         (csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers
+                         (csr_addr >= 0x3b0 && csr_addr <= 0x3ef)    // pmpaddr
                          )) {
           printf("CSR override\n");
           s->XPR.write(rd, wdata);

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -50,6 +50,7 @@ class AbstractConfig extends Config(
 
   new testchipip.WithCustomBootPin ++                               // add a custom-boot-pin to support pin-driven boot address
   new testchipip.WithBootAddrReg ++                                 // add a boot-addr-reg for configurable boot address
+  new testchipip.WithSerialTLClientIdBits(4) ++                     // support up to 1 << 4 simultaneous requests from serialTL port
   new testchipip.WithSerialTLWidth(32) ++                           // fatten the serialTL interface to improve testing performance
   new testchipip.WithDefaultSerialTL ++                             // use serialized tilelink port to external serialadapter/harnessRAM
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -21,8 +21,8 @@ class ChipLikeQuadRocketConfig extends Config(
   // Set up I/O
   //==================================
   new testchipip.WithSerialTLWidth(4) ++
+  new testchipip.WithSerialTLBackingMemory ++                                           // Backing memory is over serial TL protocol
   new chipyard.harness.WithSimAXIMemOverSerialTL ++                                     // Attach fast SimDRAM to TestHarness
-  new chipyard.config.WithSerialTLBackingMemory ++                                      // Backing memory is over serial TL protocol
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++                  // 4GB max external memory
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel
 

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -13,9 +13,6 @@ class RocketConfig extends Config(
 
 class TinyRocketConfig extends Config(
   new chipyard.iobinders.WithDontTouchIOBinders(false) ++         // TODO FIX: Don't dontTouch the ports
-  new chipyard.config.WithTLSerialLocation(
-    freechips.rocketchip.subsystem.FBUS,
-    freechips.rocketchip.subsystem.PBUS) ++                       // attach TL serial adapter to f/p busses
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
   new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
   new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
@@ -56,7 +53,6 @@ class GB1MemoryRocketConfig extends Config(
 
 // DOC include start: l1scratchpadrocket
 class ScratchpadOnlyRocketConfig extends Config(
-  new testchipip.WithSerialPBusMem ++
   new chipyard.config.WithL2TLBs(0) ++
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // remove offchip mem port
@@ -118,7 +114,7 @@ class MulticlockAXIOverSerialConfig extends Config(
     AsynchronousCrossing().sourceSync) ++
 
   new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
-  new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
+  new testchipip.WithSerialTLBackingMemory ++       // remove axi4 mem port in favor of SerialTL memory
 
   new freechips.rocketchip.subsystem.WithNBigCores(2) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel

generators/chipyard/src/main/scala/config/SodorConfigs.scala

@@ -8,7 +8,6 @@ class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
   new testchipip.WithSerialTLWidth(32) ++
-  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -18,7 +17,6 @@ class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
   new testchipip.WithSerialTLWidth(32) ++
-  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -28,7 +26,6 @@ class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
   new testchipip.WithSerialTLWidth(32) ++
-  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -38,7 +35,6 @@ class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
   new testchipip.WithSerialTLWidth(32) ++
-  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -48,7 +44,6 @@ class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
   new testchipip.WithSerialTLWidth(32) ++
-  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -58,7 +53,6 @@ class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
   new testchipip.WithSerialTLWidth(32) ++
-  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++

generators/chipyard/src/main/scala/config/SpikeConfigs.scala

@@ -27,7 +27,6 @@ class SpikeFastUARTConfig extends Config(
 class SpikeUltraFastConfig extends Config(
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
-  new testchipip.WithSerialPBusMem ++
   new chipyard.config.WithUARTFIFOEntries(128, 128) ++
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++
@@ -48,7 +47,6 @@ class SpikeUltraFastDevicesConfig extends Config(
 
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
-  new testchipip.WithSerialPBusMem ++
   new chipyard.config.WithUARTFIFOEntries(128, 128) ++
   new chipyard.config.WithMemoryBusFrequency(2) ++
   new chipyard.config.WithPeripheryBusFrequency(2) ++

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -59,27 +59,11 @@ class WithNoDebug extends Config((site, here, up) => {
   case DebugModuleKey => None
 })
 
-class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
-  case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
-})
-
 class WithTLBackingMemory extends Config((site, here, up) => {
   case ExtMem => None // disable AXI backing memory
   case ExtTLMem => up(ExtMem, site) // enable TL backing memory
 })
 
-class WithSerialTLBackingMemory extends Config((site, here, up) => {
-  case ExtMem => None
-  case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
-    memParams = {
-      val memPortParams = up(ExtMem, site).get
-      require(memPortParams.nMemoryChannels == 1)
-      memPortParams.master
-    },
-    isMemoryDevice = true
-  )}
-})
-
 class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
   case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
 })

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -40,9 +40,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
 
   // Serialized TL
   val sVal = p(SerialTLKey).get
-  require(sVal.axiMemOverSerialTLParams.isDefined)
+  val serialTLManagerParams = sVal.serialTLManagerParams.get
-  require(sVal.isMemoryDevice)
+  val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
-  val axiDomainParams = sVal.axiMemOverSerialTLParams.get
+  require(serialTLManagerParams.isMemoryDevice)
   val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
 
   withClockAndReset(clock, reset) {
@@ -56,9 +56,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
     io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset)
 
     // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
-    (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
+    (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
-      val memSize = sVal.memParams.size
+      val memSize = serialTLManagerParams.memParams.size
-      val memBase = sVal.memParams.base
+      val memBase = serialTLManagerParams.memParams.base
       val lineSize = p(CacheBlockBytes)
       val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
       mem.io.axi <> axi_port.bits

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -139,9 +139,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
 
     p(SerialTLKey).map({ sVal =>
-      require(sVal.axiMemOverSerialTLParams.isDefined)
+      val serialTLManagerParams = sVal.serialTLManagerParams.get
-      val axiDomainParams = sVal.axiMemOverSerialTLParams.get
+      val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
-      require(sVal.isMemoryDevice)
+      require(serialTLManagerParams.isMemoryDevice)
 
       val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
 
@@ -160,9 +160,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
         when (success) { th.success := true.B }
 
         // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
-        (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
+        (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
-          val memSize = sVal.memParams.size
+          val memSize = serialTLManagerParams.memParams.size
-          val memBase = sVal.memParams.base
+          val memBase = serialTLManagerParams.memParams.base
           val lineSize = p(CacheBlockBytes)
           val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
           mem.io.axi <> axi_port.bits

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -113,10 +113,9 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
     implicit val p = GetSystemParameters(system)
 
     p(SerialTLKey).map({ sVal =>
-      require(sVal.axiMemOverSerialTLParams.isDefined)
+      val serialTLManagerParams = sVal.serialTLManagerParams.get
-      val axiDomainParams = sVal.axiMemOverSerialTLParams.get
+      val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
-      require(sVal.isMemoryDevice)
+      require(serialTLManagerParams.isMemoryDevice)
-
       val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
 
       ports.map({ port =>
@@ -132,7 +131,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
         TSIBridge(th.harnessBinderClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.harnessBinderReset.asBool)
 
         // connect SimAxiMem
-        (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>
+        (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi4, edge) =>
           val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth,
                                         axi4.bits.ar.bits.addr.getWidth,
                                         axi4.bits.ar.bits.id.getWidth)

software/embench/build.sh

@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+
+set -e
+
+echo  "Building embench-iot for riscv64"
+BUILDDIR=$(pwd)/build
+mkdir -p $BUILDDIR
+
+cd embench-iot
+# use the riscv32 target, but use riscv64 compiler
+./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc --cflags="-c -O2 -ffunction-sections -mabi=lp64d -specs=htif_nano.specs" --ldflags="-Wl,-gc-sections -specs=htif_nano.specs" --user-libs="-lm" --clean -v
+
+echo "Copying binaries to $BUILDDIR"
+bmarks=("aha-mont64" "crc32" "cubic" "edn" "huffbench"
+        "matmult-int" "minver" "nbody" "nettle-aes"
+        "nettle-sha256" "nsichneu" "picojpeg"
+        "qrduino" "sglib-combined" "slre" "st"
+        "statemate" "ud" "wikisort")
+for bmark in "${bmarks[@]}"
+do
+    cp bd/src/$bmark/$bmark $BUILDDIR/
+done
+