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Have global location to store jar files (avoid issue with sbt assembly caching)

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abejgonzalez
2023-05-26 13:14:06 -07:00
parent aff98d77fe
commit b65d8ef6c6
6 changed files with 8 additions and 6 deletions
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1
.gitignore vendored
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@@ -26,3 +26,4 @@ project/metals.sbt
project/project/ project/project/
.ivy2 .ivy2
.sbt .sbt
classpath-cache/

2
sims/vcs/Makefile
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@@ -93,7 +93,7 @@ $(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
######################################################################################### #########################################################################################
.PHONY: clean clean-sim clean-sim-debug .PHONY: clean clean-sim clean-sim-debug
clean: clean:
rm -rf $(gen_dir) $(sim_prefix)-* ucli.key rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-* ucli.key
clean-sim: clean-sim:
rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key

2
sims/verilator/Makefile
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@@ -226,7 +226,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
######################################################################################### #########################################################################################
.PHONY: clean clean-sim clean-sim-debug .PHONY: clean clean-sim clean-sim-debug
clean: clean:
rm -rf $(gen_dir) $(sim_prefix)-* rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
clean-sim: clean-sim:
rm -rf $(model_dir) $(sim) rm -rf $(model_dir) $(sim)

2
sims/xcelium/Makefile
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@@ -131,7 +131,7 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
######################################################################################### #########################################################################################
.PHONY: clean clean-sim clean-sim-debug .PHONY: clean clean-sim clean-sim-debug
clean: clean:
rm -rf $(gen_dir) $(sim_prefix)-* rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
clean-sim: clean-sim:
rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log

5
variables.mk
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@@ -146,8 +146,9 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
endif endif
# classpaths # classpaths
CHIPYARD_CLASSPATH ?= $(gen_dir)/chipyard.jar CLASSPATH_CACHE ?= $(base_dir)/classpath-cache
TAPEOUT_CLASSPATH ?= $(gen_dir)/tapeout.jar CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar
TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar
# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix) # if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH)) CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH)) TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))

2
vlsi/Makefile
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@@ -171,4 +171,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
######################################################################################### #########################################################################################
.PHONY: clean .PHONY: clean
clean: clean:
rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(CLASSPATH_CACHE) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)