From 270e558272cd46a37748e79b928e9c76b83e67e9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 23 Jul 2019 22:04:12 +0000 Subject: [PATCH 01/12] Initial MIDAS2 support --- .../firechip/src/main/scala/SimConfigs.scala | 4 ++ .../src/main/scala/TargetMixins.scala | 50 ++++++++++++++++++- .../firechip/src/main/scala/Targets.scala | 12 +++-- .../src/test/scala/ScalaTestSuite.scala | 7 +-- sims/firesim | 2 +- 5 files changed, 66 insertions(+), 9 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 1118fe07..937c2877 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -52,3 +52,7 @@ class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( new FRFCFS16GBQuadRankLLC4MB3Div ++ new FireSimConfig) +class Midas2Config extends Config( + new WithMultiCycleRamModels ++ + new FireSimConfig) + diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 7b4d5d4f..535e354a 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -1,6 +1,7 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ @@ -12,7 +13,31 @@ import freechips.rocketchip.rocket.TracedInstruction import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.models.AXI4BundleWithEdge -import midas.targetutils.ExcludeInstanceAsserts +import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} + +/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ +trait HasDefaultBusConfiguration { + this: BaseSubsystem => + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges * associated with each port. This drives FASED functional model sizing @@ -104,3 +129,26 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp { ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb")) } +trait CanHaveBoomMultiCycleRegfileImp { + val outer: boom.system.BoomRocketSubsystem + val cores = outer.boomTiles.map(tile => tile.module.core) + cores.foreach({ core => + core.iregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + + if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + + }) +} +trait CanHaveRocketMultiCycleRegfileImp { + val outer: RocketSubsystem + outer.rocketTiles.foreach({ tile => + annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf)) + tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + }) +} diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 7f8bb830..34477509 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -31,7 +31,7 @@ import java.io.File *******************************************************************************/ class FireSim(implicit p: Parameters) extends RocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -54,10 +54,11 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasPeripheryIceNICModuleImpValidOnly with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with CanHaveRocketMultiCycleRegfileImp class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -78,10 +79,11 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with CanHaveRocketMultiCycleRegfileImp class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -105,9 +107,10 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions + with CanHaveBoomMultiCycleRegfileImp class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -129,6 +132,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsys with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions + with CanHaveBoomMultiCycleRegfileImp case object NumNodes extends Field[Int] diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 54848ac8..44c4bff0 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,9 +109,9 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 50 + val resetLength = 51 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1) + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { @@ -131,8 +131,9 @@ abstract class FireSimTestSuite( } class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig") -class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig") class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") { runSuite("verilator")(NICLoopbackTests) } +class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config") +class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config") diff --git a/sims/firesim b/sims/firesim index 4cd75833..a3d48a43 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4cd75833dfc1f9f796a1c5505ece6937fd253189 +Subproject commit a3d48a43a972e663e45a2ce4617a798a940d6a2b From a146d0040d4112c4b4fbe253b235481d546b4337 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 19 Aug 2019 11:15:07 -0700 Subject: [PATCH 02/12] [firechip] Add MIDAS environments for all targets --- .../firechip/src/main/scala/SimConfigs.scala | 16 +-------- .../src/main/scala/TargetConfigs.scala | 36 +++++++++++++++++-- .../firechip/src/main/scala/Targets.scala | 34 ++++++++++++------ 3 files changed, 59 insertions(+), 27 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 937c2877..6f6464dc 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -19,40 +19,26 @@ import firesim.configs._ * reconstruct what is in a particular AGFI. These tags are also used to * determine which driver to build. *******************************************************************************/ -class FireSimConfig extends Config( - new WithSerialWidget ++ - new WithUARTWidget ++ - new WithSimpleNICWidget ++ - new WithBlockDevWidget ++ - new WithDefaultMemModel ++ - new WithTracerVWidget ++ - new BasePlatformConfig) +class FireSimConfig extends Config(new BasePlatformConfig) class FireSimClockDivConfig extends Config( - new WithDefaultMemModel(clockDivision = 2) ++ new FireSimConfig) class FireSimDDR3Config extends Config( - new FCFS16GBQuadRank ++ new FireSimConfig) class FireSimDDR3LLC4MBConfig extends Config( - new FCFS16GBQuadRankLLC4MB ++ new FireSimConfig) class FireSimDDR3FRFCFSConfig extends Config( - new FRFCFS16GBQuadRank ++ new FireSimConfig) class FireSimDDR3FRFCFSLLC4MBConfig extends Config( - new FRFCFS16GBQuadRankLLC4MB ++ new FireSimConfig) class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( - new FRFCFS16GBQuadRankLLC4MB3Div ++ new FireSimConfig) class Midas2Config extends Config( new WithMultiCycleRamModels ++ new FireSimConfig) - diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9be95d89..531c067a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -10,10 +10,14 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.DebugModuleParams import boom.system.BoomTilesKey -import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig} +import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import icenet._ +import firesim.util.{EndpointKey, TieOffDebug} +import firesim.endpoints._ +import firesim.configs.WithDefaultMemModel + class WithBootROM extends Config((site, here, up) => { case BootROMParams => { val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") @@ -33,13 +37,33 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => }) class WithUARTKey extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams( + case EndpointKey => up(EndpointKey) ++ Seq(UARTEndpoint) + case PeripheryUARTKey => List(UARTParams( address = BigInt(0x54000000L), nTxEntries = 256, nRxEntries = 256)) }) +class WithSerialEndpoint extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(SerialEndpoint) +}) + +class WithTracerVEndpoint extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(TracerVEndpoint) +}) + +class WithBlockDevice extends Config( + new Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(BlockDevEndpoint, firesim.util.FASEDEndpointMatcher) + }) ++ new testchipip.WithBlockDevice +) + +class WithTieOffDebug extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(TieOffDebug) +}) + class WithNICKey extends Config((site, here, up) => { + //case EndpointKey => up(EndpointKey) ++ Seq(NICEndpoint) case NICKey => NICConfig( inBufFlits = 8192, ctrlQueueDepth = 64) @@ -97,6 +121,10 @@ class FireSimRocketChipConfig extends Config( new WithRocketL2TLBs(1024) ++ new WithPerfCounters ++ new WithoutClockGating ++ + new WithDefaultMemModel ++ + new WithSerialEndpoint ++ + new WithTracerVEndpoint ++ + new WithTieOffDebug ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -136,6 +164,10 @@ class FireSimBoomConfig extends Config( new WithBlockDevice ++ new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ + new WithDefaultMemModel ++ + new WithSerialEndpoint ++ + new WithTracerVEndpoint ++ + new WithTieOffDebug ++ // Using a small config because it has 64-bit system bus, and compiles quickly new boom.system.SmallBoomConfig) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 34477509..e592f5d1 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -17,8 +17,14 @@ import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import sifive.blocks.devices.uart._ import midas.models.AXI4BundleWithEdge +import firesim.util.IOMatchingMIDASEnvironment import java.io.File + +object FireSimValName { + implicit val valName = ValName("TestHarness") +} +import FireSimValName._ /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -30,7 +36,7 @@ import java.io.File * determine which driver to build. *******************************************************************************/ -class FireSim(implicit p: Parameters) extends RocketSubsystem +class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -44,7 +50,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimModuleImp(this) } -class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) +class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -56,8 +62,9 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp +class FireSim(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimDUT).module) -class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem +class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -70,7 +77,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimNoNICModuleImp(this) } -class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l) +class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -82,7 +89,9 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with CanHaveRocketMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem +class FireSimNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimNoNICDUT).module) + +class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -96,7 +105,7 @@ class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem override lazy val module = new FireBoomModuleImp(this) } -class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l) +class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -109,7 +118,9 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem +class FireBoom(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomDUT).module) + +class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -122,7 +133,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem override lazy val module = new FireBoomNoNICModuleImp(this) } -class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l) +class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -134,6 +145,8 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsys with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp +class FireBoomNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomNoNICDUT).module) + case object NumNodes extends Field[Int] class SupernodeIO( @@ -152,10 +165,10 @@ class SupernodeIO( } -class FireSimSupernode(implicit p: Parameters) extends Module { +class FireSimSupernodeDUT(implicit p: Parameters) extends Module { val nNodes = p(NumNodes) val nodes = Seq.fill(nNodes) { - Module(LazyModule(new FireSim).module) + Module(LazyModule(new FireSimDUT).module) } val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get)) @@ -178,3 +191,4 @@ class FireSimSupernode(implicit p: Parameters) extends Module { } } } +class FireSimSupernode(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => new FireSimSupernodeDUT) From e18e59ccda4fe1f0b053626c45560bbb1d53c066 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 6 Sep 2019 12:48:41 -0700 Subject: [PATCH 03/12] [FireSim] Use black-box instantiations of endpoints --- .../scala/DefaultFireSimEnvironment.scala | 72 +++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 27 +------ .../firechip/src/main/scala/Targets.scala | 26 ++----- 3 files changed, 78 insertions(+), 47 deletions(-) create mode 100644 generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala new file mode 100644 index 00000000..0d22e3fb --- /dev/null +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -0,0 +1,72 @@ +package firesim.firesim + +import chisel3._ +import chisel3.experimental.RawModule + +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp +import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + +import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} + +import junctions.{NastiKey, NastiParameters} +import midas.widgets.{IsEndpoint, PeekPokeEndpoint} +import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import firesim.endpoints._ +import firesim.configs.MemModelKey + +// Creates a wrapper module that instantiates endpoints based on the scala type +// of the Target (_not_ its IO). This avoids needing to duplicate environments +// (essentially test harnesses) for each target type, +// +// You could just as well create a custom environment (essentially, test +// harness) module that instantiates endpoints explicitly, or add methods to +// your target traits that instantiate the endpoint there (i.e., akin to +// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match +// on the types rather than change trait code. + +class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { + val clock = IO(Input(Clock())) + val reset = WireInit(false.B) + withClockAndReset(clock, reset) { + val target = Module(LazyModule(dutGen()).module) + val peekPokeEndpoint = PeekPokeEndpoint(reset) + // A Seq of partial functions that will instantiate the right endpoint only + // if that Mixin trait is present in the target's class instance + // + // TODO: If we like this PF approach, register them in the config instead of centralizing them here + val endpointBinders = Seq[PartialFunction[Any, Seq[IsEndpoint]]]( + { case t: HasPeripheryDebugModuleImp => + t.debug.clockeddmi.foreach({ cdmi => + cdmi.dmi.req.valid := false.B + cdmi.dmi.req.bits := DontCare + cdmi.dmi.resp.ready := false.B + cdmi.dmiClock := false.B.asClock + cdmi.dmiReset := false.B + }) + Seq() + }, + { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) }, + { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, + { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, + { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp => + (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => + (io zip node.in).map({ case (axi4Bundle, (_, edge)) => + val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, + axi4Bundle.ar.bits.addr.getWidth, + axi4Bundle.ar.bits.id.getWidth) + val fasedP = p.alterPartial({ + case NastiKey => nastiKey + case FasedAXI4Edge => Some(edge) + }) + FASEDEndpoint(axi4Bundle, reset, p(MemModelKey)(fasedP))(fasedP) + }) + }).toSeq + }, + { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) } + ) + // Apply each partial function to the DUT; collecting the generated endpoints + val endpoints = endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) + } +} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 531c067a..ac2ed1d0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -14,7 +14,6 @@ import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import icenet._ -import firesim.util.{EndpointKey, TieOffDebug} import firesim.endpoints._ import firesim.configs.WithDefaultMemModel @@ -37,33 +36,15 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => }) class WithUARTKey extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(UARTEndpoint) case PeripheryUARTKey => List(UARTParams( address = BigInt(0x54000000L), nTxEntries = 256, nRxEntries = 256)) }) -class WithSerialEndpoint extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(SerialEndpoint) -}) - -class WithTracerVEndpoint extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(TracerVEndpoint) -}) - -class WithBlockDevice extends Config( - new Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(BlockDevEndpoint, firesim.util.FASEDEndpointMatcher) - }) ++ new testchipip.WithBlockDevice -) - -class WithTieOffDebug extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(TieOffDebug) -}) +class WithBlockDevice extends Config(new testchipip.WithBlockDevice) class WithNICKey extends Config((site, here, up) => { - //case EndpointKey => up(EndpointKey) ++ Seq(NICEndpoint) case NICKey => NICConfig( inBufFlits = 8192, ctrlQueueDepth = 64) @@ -122,9 +103,6 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithSerialEndpoint ++ - new WithTracerVEndpoint ++ - new WithTieOffDebug ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -165,9 +143,6 @@ class FireSimBoomConfig extends Config( new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithSerialEndpoint ++ - new WithTracerVEndpoint ++ - new WithTieOffDebug ++ // Using a small config because it has 64-bit system bus, and compiles quickly new boom.system.SmallBoomConfig) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index e592f5d1..5b905bcc 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.config.Parameters import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.amba.axi4.AXI4Bundle @@ -16,15 +17,14 @@ import icenet._ import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import sifive.blocks.devices.uart._ -import midas.models.AXI4BundleWithEdge -import firesim.util.IOMatchingMIDASEnvironment import java.io.File object FireSimValName { - implicit val valName = ValName("TestHarness") + implicit val valName = ValName("FireSimHarness") } import FireSimValName._ + /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -40,7 +40,6 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryIceNIC @@ -54,7 +53,6 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp( with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryIceNICModuleImpValidOnly @@ -62,13 +60,10 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp( with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimDUT).module) - class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryBlockDevice @@ -81,7 +76,6 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp @@ -89,13 +83,12 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem with CanHaveRocketMultiCycleRegfileImp -class FireSimNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimNoNICDUT).module) +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT) class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryIceNIC @@ -109,7 +102,6 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryIceNICModuleImpValidOnly @@ -118,13 +110,10 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomDUT).module) - class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryBlockDevice @@ -137,7 +126,6 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp @@ -145,14 +133,12 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomNoNICDUT).module) - case object NumNodes extends Field[Int] class SupernodeIO( nNodes: Int, serialWidth: Int, - bagPrototype: HeterogeneousBag[AXI4BundleWithEdge])(implicit p: Parameters) + bagPrototype: HeterogeneousBag[midas.models.AXI4BundleWithEdge])(implicit p: Parameters) extends Bundle { val serial = Vec(nNodes, new SerialIO(serialWidth)) @@ -190,5 +176,3 @@ class FireSimSupernodeDUT(implicit p: Parameters) extends Module { n.debug.clockeddmi.get.dmi.req.bits.op := DontCare } } } - -class FireSimSupernode(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => new FireSimSupernodeDUT) From 9285155476c8f48eff9d7e64266cda8e70112337 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 6 Sep 2019 14:51:01 -0700 Subject: [PATCH 04/12] [Firechip] Add NIC endpoint; Add environments for all targets --- .../scala/DefaultFireSimEnvironment.scala | 15 ++++-- .../firechip/src/main/scala/Targets.scala | 49 +++---------------- 2 files changed, 18 insertions(+), 46 deletions(-) diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala index 0d22e3fb..8440a6da 100644 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -3,12 +3,13 @@ package firesim.firesim import chisel3._ import chisel3.experimental.RawModule -import freechips.rocketchip.config.Parameters +import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} +import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} import midas.widgets.{IsEndpoint, PeekPokeEndpoint} @@ -26,11 +27,14 @@ import firesim.configs.MemModelKey // SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match // on the types rather than change trait code. +case object NumNodes extends Field[Int](1) + class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { val clock = IO(Input(Clock())) val reset = WireInit(false.B) withClockAndReset(clock, reset) { - val target = Module(LazyModule(dutGen()).module) + // Instantiate multiple instances of the DUT to implement supernode + val targets = Seq.fill(p(NumNodes))(Module(LazyModule(dutGen()).module)) val peekPokeEndpoint = PeekPokeEndpoint(reset) // A Seq of partial functions that will instantiate the right endpoint only // if that Mixin trait is present in the target's class instance @@ -48,6 +52,7 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p Seq() }, { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) }, + { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) }, { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp => @@ -66,7 +71,9 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p }, { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) } ) - // Apply each partial function to the DUT; collecting the generated endpoints - val endpoints = endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) + // Apply each partial function to each DUT instance + for ((target) <- targets) { + endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) + } } } diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 5b905bcc..5111819f 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -60,6 +60,8 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp( with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp +class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) + class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort @@ -110,6 +112,8 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp +class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT) + class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort @@ -133,46 +137,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -case object NumNodes extends Field[Int] +class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT) -class SupernodeIO( - nNodes: Int, - serialWidth: Int, - bagPrototype: HeterogeneousBag[midas.models.AXI4BundleWithEdge])(implicit p: Parameters) - extends Bundle { - - val serial = Vec(nNodes, new SerialIO(serialWidth)) - val mem_axi = Vec(nNodes, bagPrototype.cloneType) - val bdev = Vec(nNodes, new BlockDeviceIO) - val net = Vec(nNodes, new NICIOvonly) - val uart = Vec(nNodes, new UARTPortIO) - - override def cloneType = new SupernodeIO(nNodes, serialWidth, bagPrototype).asInstanceOf[this.type] -} - - -class FireSimSupernodeDUT(implicit p: Parameters) extends Module { - val nNodes = p(NumNodes) - val nodes = Seq.fill(nNodes) { - Module(LazyModule(new FireSimDUT).module) - } - - val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get)) - - io.mem_axi.zip(nodes.map(_.mem_axi4)).foreach { - case (out, mem_axi4) => out <> mem_axi4.get - } - io.serial <> nodes.map(_.serial) - io.bdev <> nodes.map(_.bdev) - io.net <> nodes.map(_.net) - io.uart <> nodes.map(_.uart(0)) - nodes.foreach{ case n => { - n.debug.clockeddmi.get.dmi.req.valid := false.B - n.debug.clockeddmi.get.dmi.resp.ready := false.B - n.debug.clockeddmi.get.dmiClock := clock - n.debug.clockeddmi.get.dmiReset := reset.toBool - n.debug.clockeddmi.get.dmi.req.bits.data := DontCare - n.debug.clockeddmi.get.dmi.req.bits.addr := DontCare - n.debug.clockeddmi.get.dmi.req.bits.op := DontCare - } } -} +// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1 +class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) From ac8385a0c51843a4ff91bd6812b3983387fabf76 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 13 Sep 2019 00:40:50 -0700 Subject: [PATCH 05/12] [firechip] Remove unneeded FASED target Mixin --- .../scala/DefaultFireSimEnvironment.scala | 3 +- .../src/main/scala/TargetMixins.scala | 54 ------------------- .../firechip/src/main/scala/Targets.scala | 16 +++--- 3 files changed, 10 insertions(+), 63 deletions(-) diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala index 8440a6da..80750f52 100644 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -6,6 +6,7 @@ import chisel3.experimental.RawModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} @@ -55,7 +56,7 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) }, { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, - { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp => + { case t: CanHaveMasterAXI4MemPortModuleImp => (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 535e354a..bf50db80 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -38,60 +38,6 @@ trait HasDefaultBusConfiguration { } } - -/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges - * associated with each port. This drives FASED functional model sizing - */ -trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem => - val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp - - val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) => - val portName = "axi4" - val device = new MemoryDevice - - val memAXI4Node = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsWrite = TransferSizes(1, mbus.blockBytes), - supportsRead = TransferSizes(1, mbus.blockBytes), - interleavedId = Some(0))), // slave does not interleave read responses - beatBytes = memPortParams.beatBytes) - }) - - memAXI4Node := mbus.toDRAMController(Some(portName)) { - AXI4UserYanker() := AXI4IdIndexer(memPortParams.idBits) := TLToAXI4() - } - - memAXI4Node - } -} - -/** Actually generates the corresponding IO in the concrete Module */ -trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp { - val outer: CanHaveFASEDOptimizedMasterAXI4MemPort - - val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in)))) - (mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) => - (io zip node.in).foreach { case (io, (bundle, _)) => io <> bundle } - } - - def connectSimAXIMem() { - (mem_axi4 zip outer.memAXI4Node).foreach { case (io, node) => - (io zip node.in).foreach { case (io, (_, edge)) => - val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) - Module(mem.module).io.axi4.head <> io - } - } - } -} - /* Wires out tile trace ports to the top; and wraps them in a Bundle that the * TracerV endpoint can match on. */ diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 5111819f..853b54a5 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -38,7 +38,7 @@ import FireSimValName._ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -51,7 +51,7 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp @@ -64,7 +64,7 @@ class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => ne class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -76,7 +76,7 @@ class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp @@ -89,7 +89,7 @@ class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -102,7 +102,7 @@ class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp @@ -116,7 +116,7 @@ class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => n class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -128,7 +128,7 @@ class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp From 4c087b5c3f48a7870860f3226d28be833ea447cf Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 17 Sep 2019 23:50:04 -0700 Subject: [PATCH 06/12] [firechip] Remove some antiquated midas imports --- generators/firechip/src/main/scala/SimConfigs.scala | 2 -- generators/firechip/src/main/scala/TargetMixins.scala | 1 - 2 files changed, 3 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 6f6464dc..06e6aa93 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -3,8 +3,6 @@ package firesim.firesim import freechips.rocketchip.config.{Parameters, Config, Field} -import midas.{EndpointKey} -import midas.widgets.{EndpointMap} import midas.models._ import firesim.endpoints._ diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index bf50db80..1b8b5f62 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -12,7 +12,6 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} -import midas.models.AXI4BundleWithEdge import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} /** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ From 38588b67efcaefe6e9c23184fd981ab65cdf8ffb Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 19 Sep 2019 15:21:08 -0700 Subject: [PATCH 07/12] Bump FireSim, update reset delay in ScalaTests --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 44c4bff0..7a07e950 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,7 +109,7 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 51 + val resetLength = 50 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") diff --git a/sims/firesim b/sims/firesim index 92fe0e4d..9eaa0dc8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 92fe0e4def4d9bde0c5c36cd9090ef8c60fd0d45 +Subproject commit 9eaa0dc85081a06ad25b3ed21ebf63942f6c061b From 829f8fd84d073372b9081b54b5b4f05c5b8ee53b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 19 Sep 2019 15:32:09 -0700 Subject: [PATCH 08/12] [firechip] Remove unneeded HasDefaultBusConfiguration --- .../src/main/scala/TargetMixins.scala | 23 ------------------- 1 file changed, 23 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index b40a91ff..46c5f9f8 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -14,29 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} -/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ -trait HasDefaultBusConfiguration { - this: BaseSubsystem => - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - /* Wires out tile trace ports to the top; and wraps them in a Bundle that the * TracerV endpoint can match on. */ From f44f3aacbf522776f417cc0dda74acf935871f94 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 24 Sep 2019 03:04:27 +0000 Subject: [PATCH 09/12] [FireChip] Allow users to register new EndpointBinders in P --- .../scala/DefaultFireSimEnvironment.scala | 16 ++-- .../src/main/scala/EndpointBinders.scala | 92 +++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 2 + .../firechip/src/main/scala/Targets.scala | 12 +-- 4 files changed, 110 insertions(+), 12 deletions(-) create mode 100644 generators/firechip/src/main/scala/EndpointBinders.scala diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala index 80750f52..6bb53ed6 100644 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -1,3 +1,5 @@ +//See LICENSE for license details. + package firesim.firesim import chisel3._ @@ -18,19 +20,21 @@ import midas.models.{FASEDEndpoint, FasedAXI4Edge} import firesim.endpoints._ import firesim.configs.MemModelKey -// Creates a wrapper module that instantiates endpoints based on the scala type -// of the Target (_not_ its IO). This avoids needing to duplicate environments -// (essentially test harnesses) for each target type, +// Creates a wrapper FireSim harness module that instantiates endpoints based +// on the scala type of the Target (_not_ its IO). This avoids needing to +// duplicate harnesses (essentially test harnesses) for each target. // -// You could just as well create a custom environment (essentially, test -// harness) module that instantiates endpoints explicitly, or add methods to +// You could just as well create a custom harness module that instantiates +// endpoints explicitly, or add methods to // your target traits that instantiate the endpoint there (i.e., akin to // SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match // on the types rather than change trait code. +// Determines the number of times to instantiate the DUT in the harness. +// Subsumes legacy supernode support case object NumNodes extends Field[Int](1) -class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { +class DefaultFireSimHarness[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { val clock = IO(Input(Clock())) val reset = WireInit(false.B) withClockAndReset(clock, reset) { diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala new file mode 100644 index 00000000..631ad6d9 --- /dev/null +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -0,0 +1,92 @@ +//See LICENSE for license details. + +package firesim.firesim + +import chisel3._ +import chisel3.experimental.RawModule + +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + +import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} +import icenet.HasPeripheryIceNICModuleImpValidOnly + +import junctions.{NastiKey, NastiParameters} +import midas.widgets.{IsEndpoint, PeekPokeEndpoint} +import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import firesim.endpoints._ +import firesim.configs.MemModelKey + + +// A sequence of partial functions that match on the type the DUT (_not_ it's +// IO) to generate an appropriate endpoint. You can add your own endpoint by prepending +// a custom PartialFunction to this Seq +case object EndpointBinders extends Field[Seq[PartialFunction[Any, Seq[IsEndpoint]]]](Seq()) + +// Config sugar that accepts a partial function and prepends it to EndpointBinders +class RegisterEndpointBinder(pf: =>PartialFunction[Any, Seq[IsEndpoint]]) extends Config((site, here, up) => { + case EndpointBinders => pf +: up(EndpointBinders, site) +}) + +// Default FireSim Endpoint binders follow +class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => + target.debug.clockeddmi.foreach({ cdmi => + cdmi.dmi.req.valid := false.B + cdmi.dmi.req.bits := DontCare + cdmi.dmi.resp.ready := false.B + cdmi.dmiClock := false.B.asClock + cdmi.dmiReset := false.B + }) + Seq() +}) + +class WithSerialEndpoint extends RegisterEndpointBinder({ + case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p)) +}) + +class WithNICEndpoint extends RegisterEndpointBinder({ + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p)) +}) + +class WithUARTEndpoint extends RegisterEndpointBinder({ + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p)) +}) + +class WithBlockDeviceEndpoint extends RegisterEndpointBinder({ + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p)) +}) + +class WithFASEDEndpoint extends RegisterEndpointBinder({ + case t: CanHaveMasterAXI4MemPortModuleImp => + implicit val p = t.p + (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => + (io zip node.in).map({ case (axi4Bundle, (_, edge)) => + val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, + axi4Bundle.ar.bits.addr.getWidth, + axi4Bundle.ar.bits.id.getWidth) + val fasedP = p.alterPartial({ + case NastiKey => nastiKey + case FasedAXI4Edge => Some(edge) + }) + FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP) + }) + }).toSeq +}) + +class WithTracerVEndpoint extends RegisterEndpointBinder({ + case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p) +}) + +// Shorthand to register all of the provided endpoints above +class WithDefaultFireSimEndpoints extends Config( + new WithTiedOffDebug ++ + new WithSerialEndpoint ++ + new WithNICEndpoint ++ + new WithUARTEndpoint ++ + new WithBlockDeviceEndpoint ++ + new WithFASEDEndpoint ++ + new WithTracerVEndpoint +) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 91580a29..9906b24e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -107,6 +107,7 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ + new WithDefaultFireSimEndpoints ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -149,6 +150,7 @@ class FireSimBoomConfig extends Config( new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new WithDefaultFireSimEndpoints ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 6eac228d..3db3fecc 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -61,7 +61,7 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l) with HasTraceIOImp with CanHaveMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) +class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -86,7 +86,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule with CanHaveMultiCycleRegfileImp -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT) +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) class FireBoomDUT(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -113,7 +113,7 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l) with ExcludeInvalidBoomAssertions with CanHaveMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT) +class FireBoom(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomDUT) class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -138,7 +138,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModu with ExcludeInvalidBoomAssertions with CanHaveMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT) +class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomNoNICDUT) class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem with HasHierarchicalBusTopology @@ -151,5 +151,5 @@ class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModu with HasTraceGenTilesModuleImp with CanHaveMasterAXI4MemPortModuleImp -// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1 -class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) +// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 +class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) From 4c45d2e48af7ac102f38e17d21750137b7e6d4a3 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 26 Sep 2019 20:49:03 +0000 Subject: [PATCH 10/12] [firechip] Support registration of custom endpoint binders --- .../scala/DefaultFireSimEnvironment.scala | 84 ------------------- .../src/main/scala/EndpointBinders.scala | 18 +--- .../src/main/scala/TargetConfigs.scala | 4 +- .../firechip/src/main/scala/Targets.scala | 1 + sims/firesim | 2 +- 5 files changed, 6 insertions(+), 103 deletions(-) delete mode 100644 generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala deleted file mode 100644 index 6bb53ed6..00000000 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ /dev/null @@ -1,84 +0,0 @@ -//See LICENSE for license details. - -package firesim.firesim - -import chisel3._ -import chisel3.experimental.RawModule - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} -import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp - -import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} -import icenet.HasPeripheryIceNICModuleImpValidOnly - -import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint, PeekPokeEndpoint} -import midas.models.{FASEDEndpoint, FasedAXI4Edge} -import firesim.endpoints._ -import firesim.configs.MemModelKey - -// Creates a wrapper FireSim harness module that instantiates endpoints based -// on the scala type of the Target (_not_ its IO). This avoids needing to -// duplicate harnesses (essentially test harnesses) for each target. -// -// You could just as well create a custom harness module that instantiates -// endpoints explicitly, or add methods to -// your target traits that instantiate the endpoint there (i.e., akin to -// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match -// on the types rather than change trait code. - -// Determines the number of times to instantiate the DUT in the harness. -// Subsumes legacy supernode support -case object NumNodes extends Field[Int](1) - -class DefaultFireSimHarness[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { - val clock = IO(Input(Clock())) - val reset = WireInit(false.B) - withClockAndReset(clock, reset) { - // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(Module(LazyModule(dutGen()).module)) - val peekPokeEndpoint = PeekPokeEndpoint(reset) - // A Seq of partial functions that will instantiate the right endpoint only - // if that Mixin trait is present in the target's class instance - // - // TODO: If we like this PF approach, register them in the config instead of centralizing them here - val endpointBinders = Seq[PartialFunction[Any, Seq[IsEndpoint]]]( - { case t: HasPeripheryDebugModuleImp => - t.debug.clockeddmi.foreach({ cdmi => - cdmi.dmi.req.valid := false.B - cdmi.dmi.req.bits := DontCare - cdmi.dmi.resp.ready := false.B - cdmi.dmiClock := false.B.asClock - cdmi.dmiReset := false.B - }) - Seq() - }, - { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) }, - { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) }, - { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, - { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, - { case t: CanHaveMasterAXI4MemPortModuleImp => - (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => - (io zip node.in).map({ case (axi4Bundle, (_, edge)) => - val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, - axi4Bundle.ar.bits.addr.getWidth, - axi4Bundle.ar.bits.id.getWidth) - val fasedP = p.alterPartial({ - case NastiKey => nastiKey - case FasedAXI4Edge => Some(edge) - }) - FASEDEndpoint(axi4Bundle, reset, p(MemModelKey)(fasedP))(fasedP) - }) - }).toSeq - }, - { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) } - ) - // Apply each partial function to each DUT instance - for ((target) <- targets) { - endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) - } - } -} diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala index 631ad6d9..0450f8f3 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -3,9 +3,8 @@ package firesim.firesim import chisel3._ -import chisel3.experimental.RawModule -import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.config.{Field, Config} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} @@ -15,23 +14,12 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint, PeekPokeEndpoint} +import midas.widgets.{IsEndpoint} import midas.models.{FASEDEndpoint, FasedAXI4Edge} import firesim.endpoints._ import firesim.configs.MemModelKey +import firesim.util.RegisterEndpointBinder - -// A sequence of partial functions that match on the type the DUT (_not_ it's -// IO) to generate an appropriate endpoint. You can add your own endpoint by prepending -// a custom PartialFunction to this Seq -case object EndpointBinders extends Field[Seq[PartialFunction[Any, Seq[IsEndpoint]]]](Seq()) - -// Config sugar that accepts a partial function and prepends it to EndpointBinders -class RegisterEndpointBinder(pf: =>PartialFunction[Any, Seq[IsEndpoint]]) extends Config((site, here, up) => { - case EndpointBinders => pf +: up(EndpointBinders, site) -}) - -// Default FireSim Endpoint binders follow class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => target.debug.clockeddmi.foreach({ cdmi => cdmi.dmi.req.valid := false.B diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9906b24e..0e31bb56 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -19,6 +19,7 @@ import tracegen.TraceGenKey import icenet._ import firesim.endpoints._ +import firesim.util.{WithNumNodes} import firesim.configs.WithDefaultMemModel class WithBootROM extends Config((site, here, up) => { @@ -174,9 +175,6 @@ class FireSimBoomQuadCoreConfig extends Config( //********************************************************************************** //* Supernode Configurations //*********************************************************************************/ -class WithNumNodes(n: Int) extends Config((pname, site, here) => { - case NumNodes => n -}) class SupernodeFireSimRocketChipConfig extends Config( new WithNumNodes(4) ++ diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 3db3fecc..7ce143dd 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -14,6 +14,7 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.LazyModule import utilities.{Subsystem, SubsystemModuleImp} import icenet._ +import firesim.util.DefaultFireSimHarness import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp} diff --git a/sims/firesim b/sims/firesim index 9eaa0dc8..bb38ab90 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9eaa0dc85081a06ad25b3ed21ebf63942f6c061b +Subproject commit bb38ab90235847a6f9fafe55f6e1e254a510a890 From 868c2b3b6d1e34ffce40f3f70c01f1207ed13e50 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 26 Sep 2019 20:49:50 +0000 Subject: [PATCH 11/12] [firechip] Make some TracerV tests less strict --- generators/firechip/src/main/scala/TargetMixins.scala | 3 ++- generators/firechip/src/test/scala/ScalaTestSuite.scala | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 46c5f9f8..0c7d2eb9 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -1,6 +1,7 @@ package firesim.firesim import chisel3._ +import chisel3.util.Cat import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ @@ -41,7 +42,7 @@ trait HasTraceIOImp extends LazyModuleImp { // Enabled to test TracerV trace capture if (p(PrintTracePort)) { val traceprint = Wire(UInt(512.W)) - traceprint := traceIO.asUInt + traceprint := Cat(traceIO.traces.map(_.asUInt)) printf("TRACEPORT: %x\n", traceprint) } } diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 7a07e950..77415636 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,10 +109,10 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 50 + val resetLength = 51 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) - assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") + assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { assert(vPrint == sPrint) From c84c5c218e157236e3e4ea5cfca70f77a35e1187 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 27 Sep 2019 20:48:05 +0000 Subject: [PATCH 12/12] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index bb38ab90..4769e5d8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit bb38ab90235847a6f9fafe55f6e1e254a510a890 +Subproject commit 4769e5d86acf6a9508d2b5a63141dc80a6ef20a6