rename to "Chipyard"

docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst

@@ -28,7 +28,7 @@ Integrating into the Generator Build System
 -------------------------------------------
 
 While developing, you want to include Chisel code in a submodule so that it can be shared by different projects.
-To add a submodule to the REBAR framework, make sure that your project is organized as follows.
+To add a submodule to the Chipyard framework, make sure that your project is organized as follows.
 
 .. code-block:: none
 
@@ -45,7 +45,7 @@ Then add it as a submodule to under the following directory hierarchy: ``generat
     cd generators/
     git submodule add https://git-repository.com/yourproject.git
 
-Then add ``yourproject`` to the REBAR top-level build.sbt file.
+Then add ``yourproject`` to the Chipyard top-level build.sbt file.
 
 .. code-block:: scala
 
@@ -59,7 +59,7 @@ the ``example`` project, change the final line in build.sbt to the following.
 
     lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject)
 
-Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level.
+Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the Chipyard top level.
 This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files.
 
 MMIO Peripheral

docs/Getting-Started/Chipyard-Basics.rst

@@ -1,10 +1,10 @@
-REBAR Basics
+Chipyard Basics
 ===============================
 
 Generators
 -------------------------------------------
 
-The REBAR Framework currently consists of the following RTL generators:
+The Chipyard Framework currently consists of the following RTL generators:
 
 Processor Cores
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -72,7 +72,7 @@ Toolchains
   A collection of software toolchains used to develop and execute software on the RISC-V ISA.
   The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel.
   The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.).
-  Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the REBAR framework.
+  Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework.
 
 **esp-tools**
   A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension.

docs/Getting-Started/Configs-Parameters-Mixins.rst

@@ -1,7 +1,7 @@
 Configs, Parameters, Mix-ins, and Everything In Between
 ========================================================
 
-A significant portion of generators in the REBAR framework use the Rocket Chip parameter system.
+A significant portion of generators in the Chipyard framework use the Rocket Chip parameter system.
 This parameter system enables for the flexible configuration of the SoC without invasive RTL changes.
 In order to use the parameter system correctly, we will use several terms and conventions:
 
@@ -69,7 +69,7 @@ Cake Pattern
 -------------------------
 
 A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection).
-It is used in the Rocket Chip SoC library and REBAR framework in merging multiple system components and IO interfaces into a large system component.
+It is used in the Rocket Chip SoC library and Chipyard framework in merging multiple system components and IO interfaces into a large system component.
 
 :numref:`cake-example` shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design.
 

docs/Getting-Started/Development-Ecosystem.rst

@@ -1,12 +1,12 @@
 Development Ecosystem
 ===============================
 
-REBAR Approach
+Chipyard Approach
 -------------------------------------------
 
 The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts.
-REBAR hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research <https://bar.eecs.berkeley.edu/index.html>`__ can coexist and be used together.
-REBAR aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC).
+Chipyard hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research <https://bar.eecs.berkeley.edu/index.html>`__ can coexist and be used together.
+Chipyard aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC).
 
 Chisel/FIRRTL
 -------------------------------------------

docs/Getting-Started/Running-A-Simulation.rst

@@ -1,13 +1,13 @@
 Running A Simulation
 ========================================================
 
-REBAR provides support and integration for multiple simulation flows, for various user levels and requirements.
+Chipyard provides support and integration for multiple simulation flows, for various user levels and requirements.
 In the majority of cases during a digital design development process, simple software RTL simulation is needed.
 When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution.
 
 Software RTL Simulation
 ------------------------
-The REBAR framework provides wrappers for two common software RTL simulators:
+The Chipyard framework provides wrappers for two common software RTL simulators:
 the open-source Verilator simulator and the proprietary VCS simulator.
 For more information on either of these simulators, please refer to :ref:`Verilator` or :ref:`VCS`.
 The following instructions assume at least one of these simulators is installed.
@@ -97,7 +97,7 @@ FireSim enables simulations at 1000x-100000x the speed of standard software simu
 This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud.
 Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine.
 
-To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page.
+To run an FPGA-accelerated simulation using FireSim, a we need to clone the Chipyard repository (or our fork of the Chipyard repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page.
 
 After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design.
 We will work from within the ``sims/firesim`` directory.

docs/Getting-Started/index.rst

@@ -1,7 +1,7 @@
 Getting Started
 ================================
 
-These guides will walk you through the basics of the REBAR framework:
+These guides will walk you through the basics of the Chipyard framework:
 
 - First, we will go over the different configurations available.
 
@@ -13,9 +13,9 @@ Hit next to get started!
    :maxdepth: 2
    :caption: Getting Started:
 
-   REBAR-Basics
+   Chipyard-Basics
    Configs-Parameters-Mixins
    Adding-An-Accelerator-Tutorial
    Initial-Repo-Setup
    Running-A-Simulation
-   rebar-generator-mixins
+   Chipyard-Generator-Mixins