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Bump fpga-shells

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This commit is contained in:
Jerry Zhao
2023-10-24 18:24:44 -07:00
parent a4be708771
commit b4d4e54f9c
9 changed files with 16 additions and 13 deletions
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5
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -8,11 +8,11 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
import freechips.rocketchip.subsystem.{SystemBusKey}
import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
@@ -91,6 +91,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
override def provideImplicitClockToLazyChildren = true
val vcu118Outer = _outer
val reset = IO(Input(Bool())).suggestName("reset")