diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index 19e0e87c..dec6398a 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit 19e0e87cedd438f8231bb7af420cc58792735473
+Subproject commit dec6398a5c9bf7d9b80f12a9b991ee1a987337c6
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index dbae2e3b..55ebcffb 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}
 
 // don't use FPGAShell's DesignKey
 class WithNoDesignKey extends Config((site, here, up) => {
-  case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+  case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })
 
 class WithArty100TTweaks extends Config(
diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 47ffe7e0..4303a23e 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -5,12 +5,12 @@ import chisel3.util._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.prci._
 import freechips.rocketchip.subsystem.{SystemBusKey}
 
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
 
 import sifive.blocks.devices.uart._
diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala
index 7b867500..751115ec 100644
--- a/fpga/src/main/scala/nexysvideo/Configs.scala
+++ b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}
 
 // don't use FPGAShell's DesignKey
 class WithNoDesignKey extends Config((site, here, up) => {
-  case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+  case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })
 
 // DOC include start: WithNexysVideoTweaks and Rocket
diff --git a/fpga/src/main/scala/nexysvideo/Harness.scala b/fpga/src/main/scala/nexysvideo/Harness.scala
index 0cfb7110..cfc4b1cc 100644
--- a/fpga/src/main/scala/nexysvideo/Harness.scala
+++ b/fpga/src/main/scala/nexysvideo/Harness.scala
@@ -7,10 +7,10 @@ import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
 
 import sifive.blocks.devices.uart._
 
diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala
index 008e2399..75409697 100644
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -7,11 +7,12 @@ import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem.{SystemBusKey}
 import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
+import freechips.rocketchip.prci._
 
 import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks.{PLLFactoryKey}
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
 
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
@@ -88,6 +89,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
 }
 
 class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+  override def provideImplicitClockToLazyChildren = true
   val vc707Outer = _outer
 
   val reset = IO(Input(Bool())).suggestName("reset")
diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala
index 02669b79..473a015d 100644
--- a/fpga/src/main/scala/vcu118/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala
@@ -5,7 +5,7 @@ import chisel3._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell._
 import sifive.fpgashells.ip.xilinx._
 import sifive.fpgashells.shell.xilinx._
@@ -79,7 +79,7 @@ class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, va
     ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
     port.c0_sys_clk_i := sys.clock.asUInt
     port.sys_rst := sys.reset // pllReset
-    port.c0_ddr4_aresetn := !ar.reset
+    port.c0_ddr4_aresetn := !(ar.reset.asBool)
 
     // This was just copied from the SiFive example, but it's hard to follow.
     // The pins are emitted in the following order:
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 6bffc9a7..09aef9d8 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -8,11 +8,11 @@ import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
 import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
 import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
 
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
@@ -91,6 +91,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
 }
 
 class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+  override def provideImplicitClockToLazyChildren = true
   val vcu118Outer = _outer
 
   val reset = IO(Input(Bool())).suggestName("reset")
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 12398d8f..f2ead9ed 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -5,7 +5,7 @@ import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
-
+import freechips.rocketchip.prci._
 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.ip.xilinx._
 import sifive.fpgashells.shell._