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Make Passthrough clock assert more verbose

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This commit is contained in:
Jerry Zhao
2023-05-12 10:51:27 -07:00
parent 607c2b5a73
commit b42a3d4896
1 changed files with 2 additions and 1 deletions
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3
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -111,7 +111,8 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
val (bundle, edge) = clockGroupAggNode.out(0) val (bundle, edge) = clockGroupAggNode.out(0)
val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) => val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) =>
require(m.take.isDefined, s"Clock ${m.name.get} has no requested frequency") require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
|Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
val freq = m.take.get.freqMHz val freq = m.take.get.freqMHz
val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}") val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}")
b.clock := clock_io.clock b.clock := clock_io.clock