From b42a3d4896266d50b90623db03d5865b0265c073 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 May 2023 10:51:27 -0700 Subject: [PATCH] Make Passthrough clock assert more verbose --- generators/chipyard/src/main/scala/clocking/ClockBinders.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 30a5ab10..5618f582 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -111,7 +111,8 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ val (bundle, edge) = clockGroupAggNode.out(0) val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) => - require(m.take.isDefined, s"Clock ${m.name.get} has no requested frequency") + require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency + |Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin) val freq = m.take.get.freqMHz val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}") b.clock := clock_io.clock