diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index 567cc2f7..65b73015 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -122,3 +122,7 @@ class WithNoTileResetSetters extends Config((site, here, up) => {
 class WithNoResetSynchronizers extends Config((site, here, up) => {
   case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
 })
+
+class WithNoClockTap extends Config((site, here, up) => {
+  case ClockTapKey => None
+})
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 16d5281b..cf0ed66e 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -84,6 +84,7 @@ class WithMinimalFireSimDesignTweaks extends Config(
   new chipyard.harness.WithHarnessBinderClockFreqMHz(1000.0) ++
   new chipyard.harness.WithClockFromHarness ++
   new chipyard.harness.WithResetFromHarness ++
+  new chipyard.config.WithNoClockTap ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
   new WithBootROM ++
@@ -98,6 +99,8 @@ class WithMinimalFireSimDesignTweaks extends Config(
 // Non-frequency tweaks that are generally applied to all firesim configs
 class WithFireSimDesignTweaks extends Config(
   new WithMinimalFireSimDesignTweaks ++
+  // Required: Remove the debug clock tap, this breaks compilation of target-level sim in FireSim
+  new chipyard.config.WithNoClockTap ++
   // Required: Bake in the default FASED memory model
   new WithDefaultMemModel ++
   // Optional: reduce the width of the Serial TL interface