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Merge pull request #1884 from ucb-bar/gcd_io

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Add GCD IOBinders examples
This commit is contained in:
Jerry Zhao
2024-05-29 14:55:17 -07:00
committed by GitHub
parent d523df516b 3c31faef7b
commit b355a52ff0
3 changed files with 12 additions and 0 deletions
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1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -59,6 +59,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithNICIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++
new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithGCDBusyPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++ new chipyard.iobinders.WithNMITiedOff ++

9
generators/chipyard/src/main/scala/iobinders/IOBinders.scala
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@@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO} import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule} import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
import chipyard.example.{CanHavePeripheryGCD}
import scala.reflect.{ClassTag} import scala.reflect.{ClassTag}
@@ -540,3 +541,11 @@ class WithNMITiedOff extends ComposeIOBinder({
(Nil, Nil) (Nil, Nil)
} }
}) })
class WithGCDBusyPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
val io_gcd_busy = IO(Output(Bool()))
io_gcd_busy := busy
(Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
}.getOrElse((Nil, Nil))
})

2
generators/chipyard/src/main/scala/iobinders/Ports.scala
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@@ -109,3 +109,5 @@ case class JTAGResetPort (val getIO: () => Reset)
case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle]) case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle])
extends Port[HeterogeneousBag[TLBundle]] extends Port[HeterogeneousBag[TLBundle]]
case class GCDBusyPort (val getIO: () => Bool)
extends Port[Bool]