Rocket Chip Stage/Phase Bump (#503)

[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules

generators/tracegen/src/main/scala/System.scala

@@ -49,4 +49,3 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
 class TraceGenSystemModuleImp(outer: TraceGenSystem)
   extends BaseSubsystemModuleImp(outer)
   with HasTraceGenTilesModuleImp
-  with CanHaveMasterAXI4MemPortModuleImp