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Rocket Chip Stage/Phase Bump (#503)

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[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
This commit is contained in:
David Biancolin
2020-04-08 14:47:57 -07:00
parent 003bc4afcf
commit b303cf6e81
38 changed files with 406 additions and 256 deletions
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31
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -8,7 +8,7 @@ import chisel3.experimental.annotate
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem}
import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
@@ -56,19 +56,17 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
class WithFASEDBridge extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => {
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
implicit val p = system.p
(system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) =>
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
axi4Bundle.ar.bits.addr.getWidth,
axi4Bundle.ar.bits.id.getWidth)
FASEDBridge(system.clock, axi4Bundle, system.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
})
(system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
axi4.ar.bits.addr.getWidth,
axi4.ar.bits.id.getWidth)
FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
})
Nil
}
@@ -116,9 +114,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({
class WithTiedOffSystemDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
Debug.tieoffDebug(system.debug, system.psd)
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
// tieoffDebug doesn't actually tie everything off :/
system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
system.debug.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
d.dmactiveAck := DontCare
}
Nil
}
})