Rocket Chip Stage/Phase Bump (#503)

[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -8,7 +8,7 @@ import chisel3.experimental.annotate
 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp}
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem}
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
@@ -56,19 +56,17 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
 
 
 class WithFASEDBridge extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPortModuleImp) => {
+  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
     implicit val p = system.p
-    (system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) =>
-      (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
-        val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
-                                       axi4Bundle.ar.bits.addr.getWidth,
-                                       axi4Bundle.ar.bits.id.getWidth)
-        FASEDBridge(system.clock, axi4Bundle, system.reset.toBool,
-          CompleteConfig(p(firesim.configs.MemModelKey),
-                         nastiKey,
-                         Some(AXI4EdgeSummary(edge)),
-                         Some(MainMemoryConsts.globalName)))
-      })
+    (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
+      val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
+                                     axi4.ar.bits.addr.getWidth,
+                                     axi4.ar.bits.id.getWidth)
+      FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
+        CompleteConfig(p(firesim.configs.MemModelKey),
+                       nastiKey,
+                       Some(AXI4EdgeSummary(edge)),
+                       Some(MainMemoryConsts.globalName)))
     })
     Nil
   }
@@ -116,9 +114,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({
 
 class WithTiedOffSystemDebug extends OverrideIOBinder({
   (system: HasPeripheryDebugModuleImp) => {
-    Debug.tieoffDebug(system.debug, system.psd)
+    Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
     // tieoffDebug doesn't actually tie everything off :/
-    system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
+    system.debug.foreach { d => 
+      d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
+      d.dmactiveAck := DontCare
+    }
     Nil
   }
 })

generators/firechip/src/main/scala/FireSim.scala

@@ -34,14 +34,24 @@ class FireSim(implicit val p: Parameters) extends RawModule {
   val reset = WireInit(false.B)
   withClockAndReset(clock, reset) {
     // Instantiate multiple instances of the DUT to implement supernode
-    val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
+    val targets = Seq.fill(p(NumNodes)) {
+      // It's not a RC bump without some hacks...
+      // Copy the AsyncClockGroupsKey to generate a fresh node on each
+      // instantiation of the dut, otherwise the initial instance will be
+      // reused across each node
+      import freechips.rocketchip.subsystem.AsyncClockGroupsKey
+      val lazyModule = p(BuildSystem)(p.alterPartial({
+        case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
+      }))
+      (lazyModule, Module(lazyModule.module))
+    }
     val peekPokeBridge = PeekPokeBridge(clock, reset)
     // A Seq of partial functions that will instantiate the right bridge only
-    // if that Mixin trait is present in the target's class instance
+    // if that Mixin trait is present in the target's LazyModule class instance
     //
     // Apply each partial function to each DUT instance
-    for ((target) <- targets) {
-      p(IOBinders).values.map(_(target))
+    for ((lazyModule, module) <- targets) {
+      p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
       NodeIdx.increment()
     }
   }

generators/firechip/src/main/scala/FireSimMulticlockPOC.scala

@@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config
 class HalfRateUncore extends WithSingleRationalTileDomain(2,1)
 
 class WithFiresimMulticlockTop extends Config((site, here, up) => {
-  case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module)
+  case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system")
 })
 
 // Complete Config
@@ -88,16 +88,19 @@ class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
   val reset = WireInit(false.B)
   withClockAndReset(refClock, reset) {
     // Instantiate multiple instances of the DUT to implement supernode
-    val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
+    val targets = Seq.fill(p(NumNodes)) {
+      val lazyModule = p(BuildSystem)(p)
+      (lazyModule, Module(lazyModule.module))
+    }
     val peekPokeBridge = PeekPokeBridge(refClock, reset)
     // A Seq of partial functions that will instantiate the right bridge only
     // if that Mixin trait is present in the target's class instance
     //
     // Apply each partial function to each DUT instance
-    for ((target) <- targets) {
-      p(IOBinders).values.map(_(target))
+    for ((lazyModule, module) <- targets) {
+      p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
     }
-    targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
+    targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks })
   }
 }
 

generators/firechip/src/main/scala/Generator.scala

@@ -9,7 +9,7 @@ import chisel3.internal.firrtl.{Circuit, Port}
 
 import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
 import freechips.rocketchip.devices.debug.DebugIO
-import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
+import midas.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
 import freechips.rocketchip.system.DefaultTestSuites._
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
 import freechips.rocketchip.config.Parameters
@@ -24,9 +24,11 @@ import chipyard.TestSuiteHelper
 
 trait HasTestSuites {
   def addTestSuites(targetName: String, params: Parameters) {
-    TestSuiteHelper.addRocketTestSuites(params)
-    TestSuiteHelper.addBoomTestSuites(params)
-    TestSuiteHelper.addArianeTestSuites(params)
+    val suiteHelper = new TestSuiteHelper
+    suiteHelper.addRocketTestSuites(params)
+    suiteHelper.addBoomTestSuites(params)
+    suiteHelper.addArianeTestSuites(params)
+    TestGeneration.addSuites(suiteHelper.suites.values.toSeq)
     TestGeneration.addSuite(FastBlockdevTests)
     TestGeneration.addSuite(SlowBlockdevTests)
     if (!targetName.contains("NoNIC"))
@@ -47,7 +49,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
   /** Output software test Makefrags, which provide targets for integration testing. */
   def generateTestSuiteMakefrags {
     addTestSuites(names.topModuleClass, targetParams)
-    writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites
+    writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites
   }
 
   // Output miscellaneous files produced as a side-effect of elaboration
@@ -68,12 +70,3 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
   generateTestSuiteMakefrags
   generateArtefacts
 }
-
-// For now, provide a separate generator app when not specifically building for FireSim
-object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
-  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-  generateFirrtl
-  generateAnno
-  generateTestSuiteMakefrags
-  generateArtefacts
-}

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -41,7 +41,7 @@ class WithBootROM extends Config((site, here, up) => {
 })
 
 class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => {
-  case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
+  case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
 })
 
 

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -137,7 +137,7 @@ abstract class FireSimTestSuite(
 }
 
 class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config")
-class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
+class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config")
 class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
   runSuite("verilator")(NICLoopbackTests)
 }