Rocket Chip Stage/Phase Bump (#503)

[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -21,7 +21,7 @@ import hwacha.{Hwacha}
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 
-import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset}
+import chipyard.{BuildTop, BuildSystem}
 
 /**
  * TODO: Why do we need this?
@@ -66,7 +66,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 })
 
 class WithTracegenSystem extends Config((site, here, up) => {
-  case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module)
+  case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p))
 })
 
 
@@ -150,13 +150,3 @@ class WithControlCore extends Config((site, here, up) => {
     )
   case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })
-
-
-/**
- * Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to
- * the top-level reset, allowing it to be asynchronous with the clock.
- * NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config
- */
-class WithChipTopCaughtReset extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top"))
-})