diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 3c57d64c..98c770ad 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("boom" "hwacha" "icenet" "sha3" "rocket-chip" "sifive-blocks" "sifive-cache" "testchipip" "gemmini") +submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then @@ -80,12 +80,12 @@ dir="toolchains" branches=("master") search -submodules=("spec2017" "coremark") +submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017") dir="software" branches=("master") search -submodules=("axe" "barstools" "torture" "dsptools" "chisel-testers" "treadle" "firrtl-interpreter") +submodules=("DRAMSim2" "axe" "barstools" "chisel-testers" "dsptools" "firrtl-interpreter" "torture" "treadle") dir="tools" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then @@ -95,6 +95,11 @@ else fi search +submodules=("dromajo-src") +dir="tools/dromajo" +branches=("master") +search + submodules=("firesim") dir="sims" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] diff --git a/CHANGELOG.md b/CHANGELOG.md index f9447b0e..38ea7e6e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,65 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.3.0] - 2020-05-31 + +A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/500 + +### Added +* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. (#480) +* A new BuildSystem key has been added, which by default builds DigitalTop (#480) +* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). (#480) +* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. (#480) +* CI now checks documentation changes (#485) +* Support FireSim multi-clock (#468) +* Allows make variables to be injected into build system (#499) +* Various documentation/comment updates (#511,#517,#518,#537,#533,#542,#570,#569) +* DSPTools documentation and example (#457, #568) +* Support for no UART configs (#536) +* Assemble firrtl-test.jar (#551) +* Add SPI flash configurations (#546) +* Add Dromajo + FireSim Dromajo simulation support (#523, #553, #560) +* NVDLA integration (#505, #559, #580) +* Add support for Hammer Sim (#512,#581,#580,#582) + +### Changed +* Bump FireSim to version 1.10 (#574,#586) +* Bump BOOM to version 3.0 (#523, #574,#580) +* Bump Gemmini to version 0.3 (#575, #579) +* Bump SPEC17 workload (#504, #574) +* Bump Hwacha for fixes (#580) +* Bump SHA3 for Linux 5.7rc3 support (#580) +* Bump Rocket Chip to commit 1872f5d (including stage/phase compilation) (#503,#544) +* Bump FireMarshal to version 1.9.0 (#574) +* Chisel 3.3 and FIRRTL 1.3 (#503,#544) +* BuildTop now builds a ChipTop dut module in the TestHarness by default (#480) +* The default for the TOP make variable is now ChipTop (was Top) (#480) +* Top has been renamed to DigitalTop (#480) +* Bump libgloss (#508, #516, #580) +* The default version of Verilator has changed to v4.034 (#547). Since this release adds enhanced support for Verilog timescales, the build detects if Verilator v4.034 or newer is visible in the build environment and sets default timescale flags appropriately. +* Use Scalatests for FireSim CI (#528) +* Cleanup Ariane pre-processing (#505) +* Modify Issue Template to be more explicit (#557) +* FireChip uses Chipyard generator (#554) +* Have all non-synthesizeable constructs in test harness (#572) + +### Fixed +* Aligned esp-tools spike with Gemmini (#509) +* Fix debug rule in Verilator (#513) +* Clean up SBT HTTP warnings (#526,#549) +* Artefacts dropped in FireSim (#534) +* Working IceNet + TestChipIP Unit Tests (#525) +* Don't initialize non-existent Midas submodule (#552) +* Verilator now supports +permissive similar to VCS (#565) +* Fix direction of IOCell OE (#586) + +### Deprecated +* N/A + +### Removed +* N/A + + ## [1.2.0] - 2020-03-14 A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418 @@ -59,7 +118,7 @@ A more detailed account of everything included is included in the dev to master * FireSim release 1.8.0 * FireMarshal release 1.8.0 * BOOM release 2.2.3 (PR #397) -* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls. +* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls. * Add toolchain specific `env.sh` (PR #304) * `run-binary`-like interface now dumps `.log` (stdout) and `.out` (stderr) files (PR #308) * Split the VLSI build dir on type of design (PR #331) diff --git a/generators/ariane b/generators/ariane index d914fc8f..651134f3 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit d914fc8f0320ba5b087d515b25baf98959b0facb +Subproject commit 651134f3c43ff8c0fa55a0f65faeb12b9500fcfa diff --git a/generators/boom b/generators/boom index f1a20b1b..d77c2c3f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f1a20b1b3ea7f47a4bb530d4fc44091519249731 +Subproject commit d77c2c3ff648bd5b18a932aa9f6b64dead7e3476 diff --git a/generators/hwacha b/generators/hwacha index 2706502d..a989b697 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit 2706502daf862c9a7a39126eb7e7209eaf984f76 +Subproject commit a989b69759137802b4c39e9ddebb90427455fb79 diff --git a/generators/sha3 b/generators/sha3 index cec8db9d..a94dcf3a 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit cec8db9d6b3a602771cae63eaf6705baa3492f6a +Subproject commit a94dcf3ae0a0440aade96bcdaa4da685352ae704 diff --git a/generators/testchipip b/generators/testchipip index b02bd8ea..4b15061b 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b02bd8eacaffe425811bd3fd8ef7d30772ae3cb7 +Subproject commit 4b15061b6fe77f6793603f799751f1f988144ef7 diff --git a/sims/firesim b/sims/firesim index 3143253d..c2d8e3a4 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3143253dda0292643f2953087638ae43e98559f4 +Subproject commit c2d8e3a46e59222e115a1fdaa7267592e1d3c503 diff --git a/software/firemarshal b/software/firemarshal index 141a3d36..6c6a08f9 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 141a3d366f4ff9ce245192c23e5cc2ad8897bc19 +Subproject commit 6c6a08f9790c660823e9f858ca87f93b2502fa44 diff --git a/software/nvdla-workload b/software/nvdla-workload index 88b09e01..30290c3e 160000 --- a/software/nvdla-workload +++ b/software/nvdla-workload @@ -1 +1 @@ -Subproject commit 88b09e0171bdf6b3a77f711c2c8015dc727e460b +Subproject commit 30290c3ed8014577fa2ad234fa1b731a082299fb diff --git a/toolchains/libgloss b/toolchains/libgloss index a88e50f2..04b24976 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit a88e50f2e1b0411e0a7d5e5c29d5b40117560912 +Subproject commit 04b249764b1bc0b784b9f7ff422084f4b53a07ef diff --git a/tools/barstools b/tools/barstools index c4e5f66c..7e6e19b8 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 +Subproject commit 7e6e19b8adf3b625b31b09173ecae5f634c83e1b diff --git a/vlsi/Makefile b/vlsi/Makefile index a724f6f1..b7e76c50 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -32,6 +32,7 @@ ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= example.yml HAMMER_EXEC ?= ./example-vlsi VLSI_TOP ?= $(TOP) +VLSI_HARNESS_DUT_NAME ?= dut VLSI_OBJ_DIR ?= $(vlsi_dir)/build ifneq ($(CUSTOM_VLOG), ) OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) @@ -96,8 +97,10 @@ SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk -$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) mkdir -p $(dir $@) + mkdir -p $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY)) + ln -sf $(base_dir)/generators/testchipip/src/main/resources/dramsim2_ini $(OBJ_DIR)/$(HAMMER_SIM_RUN_DIR)/$(notdir $(BINARY))/dramsim2_ini echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ @@ -117,7 +120,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " defines_meta: 'append'" >> $@ echo " compiler_opts:" >> $@ - for x in $(filter-out -CC,$(VCS_CC_OPTS)); do \ + for x in $(filter-out "",$(filter-out -CC,$(VCS_CC_OPTS))); do \ echo ' - "'$$x'"' >> $@; \ done echo " compiler_opts_meta: 'append'" >> $@ @@ -129,7 +132,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " execution_flags_meta: 'append'" >> $@ echo " benchmarks: ['$(BINARY)']" >> $@ - echo " tb_dut: 'testHarness.top'" >> $@ + echo " tb_dut: 'testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) @@ -152,11 +155,10 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_comm POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk -LOWER_VLSI_TOP = $(shell echo $(VLSI_TOP) | tr A-Z a-z) $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ - echo " tb_dut: 'testHarness/$(LOWER_VLSI_TOP)'" >> $@ + echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ echo " saifs: [" >> $@ echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ diff --git a/vlsi/hammer-mentor-plugins b/vlsi/hammer-mentor-plugins index 33ccdccf..67f57f12 160000 --- a/vlsi/hammer-mentor-plugins +++ b/vlsi/hammer-mentor-plugins @@ -1 +1 @@ -Subproject commit 33ccdccf2c04a26cceeeb03a29b9cfad38908328 +Subproject commit 67f57f120031e8c23d3d165f56c3a3c7a4064aa4 diff --git a/vlsi/power.mk b/vlsi/power.mk index d1c56e2c..383da5f0 100644 --- a/vlsi/power.mk +++ b/vlsi/power.mk @@ -3,4 +3,4 @@ power-par: $(POWER_CONF) sim-par power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) redo-power-par: $(POWER_CONF) redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -$(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) +$(OBJ_DIR)/power-par-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 6abd7995..6de46a90 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -2,16 +2,19 @@ # Update hammer top-level sim targets to include our generated sim configs redo-sim-rtl: $(SIM_CONF) redo-sim-rtl: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-rtl: override HAMMER_SIM_RUN_DIR = sim-rtl-rundir redo-sim-rtl-debug: $(SIM_DEBUG_CONF) redo-sim-rtl redo-sim-rtl-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-syn: $(SIM_CONF) redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-par: $(SIM_CONF) redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug @@ -19,18 +22,21 @@ redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) sim-rtl: $(SIM_CONF) sim-rtl: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-rtl: override HAMMER_SIM_RUN_DIR = sim-rtl-rundir sim-rtl-debug: $(SIM_DEBUG_CONF) sim-rtl sim-rtl-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) +$(OBJ_DIR)/sim-rtl-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-syn: $(SIM_CONF) sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) $(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-par: $(SIM_CONF) sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir sim-par-debug: $(SIM_DEBUG_CONF) sim-par sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) sim-par-timing-debug: $(SIM_TIMING_CONF) sim-par-debug