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Use Chipyard configs as base (Arty)

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This commit is contained in:
abejgonzalez
2020-11-05 20:44:48 -08:00
parent 9a5b67bf8c
commit b0fc0457aa
3 changed files with 16 additions and 19 deletions
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29
fpga/src/main/scala/arty/Configs.scala
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@@ -11,6 +11,8 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem} import chipyard.{BuildSystem}
class WithDefaultPeripherals extends Config((site, here, up) => { class WithDefaultPeripherals extends Config((site, here, up) => {
@@ -22,29 +24,20 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
idcodePartNum = 0x000, idcodePartNum = 0x000,
idcodeManufId = 0x489, idcodeManufId = 0x489,
debugIdleCycles = 5) debugIdleCycles = 5)
case SerialTLKey => None // remove serialized tl port
}) })
class TinyRocketArtyConfig extends Config( class WithArtyTweaks extends Config(
new WithArtyJTAGHarnessBinder ++ new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++ new WithArtyUARTHarnessBinder ++
new WithArtyResetHarnessBinder ++ new WithArtyResetHarnessBinder ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new WithResetPassthrough ++ new WithResetPassthrough ++
new WithDefaultPeripherals ++ new WithDefaultPeripherals ++
new chipyard.config.WithNoSubsystemDrivenClocks ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.With1TinyCore ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithIncoherentBusTopology)
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ class TinyRocketArtyConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new WithArtyTweaks ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new chipyard.TinyRocketConfig)
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

2
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -59,7 +59,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
} }
}) })
class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) { withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_txd_in, ports.head.txd) IOBUF(th.uart_txd_in, ports.head.txd)

4
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -10,6 +10,10 @@ class RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class TinyRocketConfig extends Config(
new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
new chipyard.config.AbstractConfig)
class HwachaRocketConfig extends Config( class HwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++ new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator