Use Chipyard configs as base (Arty)

2020-11-05 20:44:48 -08:00
parent 9a5b67bf8c
commit b0fc0457aa
3 changed files with 16 additions and 19 deletions
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -59,7 +59,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
  }
 })

-class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
+class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
  (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
    withClockAndReset(th.clock_32MHz, th.ck_rst) {
      IOBUF(th.uart_txd_in,  ports.head.txd)