From 7c55ff39ccf93df91ebc3de33cd407d4e186d22e Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Sun, 31 Dec 2023 14:40:10 -0800 Subject: [PATCH 1/7] Add chipid port --- generators/chipyard/src/main/scala/DigitalTop.scala | 1 + .../chipyard/src/main/scala/config/AbstractConfig.scala | 3 +++ .../chipyard/src/main/scala/harness/HarnessBinders.scala | 7 +++++++ .../chipyard/src/main/scala/iobinders/IOBinders.scala | 9 +++++++++ generators/chipyard/src/main/scala/iobinders/Ports.scala | 3 +++ 5 files changed, 23 insertions(+) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 879ede57..3a0e2fa9 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter + with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 70770491..ec3c685e 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -23,6 +23,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present + new chipyard.harness.WithChipIdPinFromHarness ++ // drive chip id pin with a plusarg, if chip id pin is present new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness @@ -36,6 +37,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithGPIOCells ++ new chipyard.iobinders.WithSPIFlashIOCells ++ new chipyard.iobinders.WithExtInterruptIOCells ++ + new chipyard.iobinders.WithChipIdPin ++ new chipyard.iobinders.WithCustomBootPin ++ // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop @@ -63,6 +65,7 @@ class AbstractConfig extends Config( new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus + new testchipip.soc.WithChipIdPin ++ // add a chip id pin for setting chip id in multi-chip configs new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index d70519b3..5549d9c4 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -252,6 +252,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ } }) +//TODO: Allow setting from harness with chipId argument, hardcoding is temporary hack +class WithChipIdPinFromHarness extends HarnessBinder({ + case (th: HasHarnessInstantiators, port: ChipIdPort) => { + port.io := 0.U + } +}) + class WithSimUARTToUARTTSI extends HarnessBinder({ case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => { UARTAdapter.connect(Seq(port.io), diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 309ec004..de7f2867 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -27,6 +27,7 @@ import barstools.iocell.chisel._ import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} import testchipip.spi.{SPIChipIO} import testchipip.boot.{CanHavePeripheryCustomBootPin} +import testchipip.soc.{CanHavePeripheryChipIdPin} import testchipip.util.{ClockedIO} import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO} import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig} @@ -355,6 +356,14 @@ class WithSerialTLIOCells extends OverrideIOBinder({ } }) +class WithChipIdPin extends OverrideIOBinder({ + (system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true) + (Seq(ChipIdPort(() => port)), cells) + }).getOrElse(Nil, Nil) +}) + class WithSerialTLPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index 627693aa..6b327a18 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -76,6 +76,9 @@ case class JTAGPort (val getIO: () => JTAGChipIO) case class SerialTLPort (val getIO: () => Data, val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int) extends Port[Data] +case class ChipIdPort (val getIO: () => UInt) + extends Port[UInt] + case class UARTTSIPort (val getIO: () => UARTTSIIO) extends Port[UARTTSIIO] From fcf9139009dedf437c07977e5bfcd4c01c9bca2e Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Sun, 31 Dec 2023 14:43:50 -0800 Subject: [PATCH 2/7] bump tcip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index e844c51a..28a4d01b 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e844c51a084aebd89968166bab421dda87a1e693 +Subproject commit 28a4d01b1130b76ea725850fe8b600f9847b6cb8 From e7ed33244ab8f187ab04c5563ab3f5c3fea0a5c1 Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Mon, 1 Jan 2024 13:16:53 -0800 Subject: [PATCH 3/7] fix naming --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 5 ++--- .../chipyard/src/main/scala/harness/HarnessBinders.scala | 4 ++-- generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index ec3c685e..8a328daf 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -23,7 +23,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present - new chipyard.harness.WithChipIdPinFromHarness ++ // drive chip id pin with a plusarg, if chip id pin is present + new chipyard.harness.WithDriveChipIdPin ++ // drive chip id pin from harness binder, if chip id pin is present new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness @@ -37,7 +37,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithGPIOCells ++ new chipyard.iobinders.WithSPIFlashIOCells ++ new chipyard.iobinders.WithExtInterruptIOCells ++ - new chipyard.iobinders.WithChipIdPin ++ + new chipyard.iobinders.WithChipIdIOCells ++ new chipyard.iobinders.WithCustomBootPin ++ // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop @@ -65,7 +65,6 @@ class AbstractConfig extends Config( new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus - new testchipip.soc.WithChipIdPin ++ // add a chip id pin for setting chip id in multi-chip configs new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 5549d9c4..aeaec1c7 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -252,8 +252,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ } }) -//TODO: Allow setting from harness with chipId argument, hardcoding is temporary hack -class WithChipIdPinFromHarness extends HarnessBinder({ +//TODO: Set with chipId argument to harness binder, hardcoding is temporary hack +class WithDriveChipIdPin extends HarnessBinder({ case (th: HasHarnessInstantiators, port: ChipIdPort) => { port.io := 0.U } diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index de7f2867..64b1296e 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -356,7 +356,7 @@ class WithSerialTLIOCells extends OverrideIOBinder({ } }) -class WithChipIdPin extends OverrideIOBinder({ +class WithChipIdIOCells extends OverrideIOBinder({ (system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p => val sys = system.asInstanceOf[BaseSubsystem] val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true) From 8a4fc7c82f4f5fbfedea44b2d1ee813f27d65c7e Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Tue, 2 Jan 2024 14:23:07 -0800 Subject: [PATCH 4/7] [ci skip] update docs with chip id pin --- docs/Generators/TestChipIP.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 2c382d4f..32e76f5b 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -92,3 +92,15 @@ The SPI flash model is a device that models a simple SPI flash device. It curren only supports single read, quad read, single write, and quad write instructions. The memory is backed by a file which is provided using ``+spiflash#=``, where ``#`` is the SPI flash ID (usually ``0``). + +Chip ID Pin +--------------- + +The chip ID pin sets the chip ID for the chip it is added to. This is most useful in +multi-chip configs. The pin value is driven by the chip ID value set in the harness +binder and the chip ID value can be read through MMIO at the address ``0x2000`` by default. + +The pin can be added to a system with the ``testchipip.soc.WithChipIdPin`` config. The pin +width and MMIO address are parameterizable and can be set by passing ``ChipIdPinParams`` as an +argument to the config. The width can additionally be set using the ``testchipip.soc.WithChipIdPinWidth`` +config. From 67faf0c3e350fc9e90dd23d112ab72c026f40a00 Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Fri, 12 Jan 2024 11:39:54 -0800 Subject: [PATCH 5/7] Use harness binder chipId to support multi-chip id pins --- .../chipyard/src/main/scala/config/ChipletConfigs.scala | 1 + .../chipyard/src/main/scala/harness/HarnessBinders.scala | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala index e07aa73d..a7d2113f 100644 --- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala @@ -11,6 +11,7 @@ import testchipip.soc.{OBUS} // Simple design which exposes a second serial-tl port that can connect to another instance of itself class SymmetricChipletRocketConfig extends Config( + new testchipip.soc.WithChipIdPin ++ // Add pin to identify chips new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims new testchipip.serdes.WithSerialTL(Seq( testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index aeaec1c7..11fa670d 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -254,8 +254,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ //TODO: Set with chipId argument to harness binder, hardcoding is temporary hack class WithDriveChipIdPin extends HarnessBinder({ - case (th: HasHarnessInstantiators, port: ChipIdPort) => { - port.io := 0.U + case (th: HasHarnessInstantiators, port: ChipIdPort, chipId: Int) => { + port.io := chipId.U } }) From 47322af3c0768d4abd68efd95bb915247980b622 Mon Sep 17 00:00:00 2001 From: Ella Schwarz Date: Sun, 14 Jan 2024 14:47:12 -0800 Subject: [PATCH 6/7] Add assert to check that chip id pin is wide enough --- generators/chipyard/src/main/scala/harness/HarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 11fa670d..7ea74cee 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -252,9 +252,9 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ } }) -//TODO: Set with chipId argument to harness binder, hardcoding is temporary hack class WithDriveChipIdPin extends HarnessBinder({ case (th: HasHarnessInstantiators, port: ChipIdPort, chipId: Int) => { + assert(chipId < math.pow(2, port.io.getWidth), "ID Pin is not wide enough") port.io := chipId.U } }) From 565c187549bb6d457623a7eed8a4d1dbbb77e140 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 16 Jan 2024 10:15:53 -0800 Subject: [PATCH 7/7] Switch static assert to require --- generators/chipyard/src/main/scala/harness/HarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 7ea74cee..59d4110d 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -254,7 +254,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ class WithDriveChipIdPin extends HarnessBinder({ case (th: HasHarnessInstantiators, port: ChipIdPort, chipId: Int) => { - assert(chipId < math.pow(2, port.io.getWidth), "ID Pin is not wide enough") + require(chipId < math.pow(2, port.io.getWidth), "ID Pin is not wide enough") port.io := chipId.U } })