Add help section to makefiles + Reorganize
This commit is contained in:
Abraham Gonzalez
@@ -25,7 +25,10 @@ sim_prefix = simv
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
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include $(base_dir)/vcs.mk
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PERMISSIVE_ON=+permissive
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PERMISSIVE_OFF=+permissive-off
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WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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.PHONY: default debug
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default: $(sim)
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@@ -36,22 +39,97 @@ debug: $(sim_debug)
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#########################################################################################
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include $(base_dir)/common.mk
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#########################################################################################
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# verilator-specific user-interface variables and commands
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#########################################################################################
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HELP_COMPILATION_VARIABLES +=
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HELP_COMMANDS += \
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" default = compiles non-debug simulator [./$(shell basename $(sim))]" \
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" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \
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" clean = remove all debug/non-debug simulators and intermediate files" \
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" clean-sim = removes non-debug simulator and verilator-generated files" \
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" clean-sim-debug = removes debug simulator and verilator-generated files"
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#########################################################################################
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# vcs binary and arguments
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#########################################################################################
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VCS = vcs -full64
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VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES)
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PREPROC_DEFINES = \
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+define+VCS \
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+define+CLOCK_PERIOD=1.0 \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN
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VCS_NONCC_OPTS = \
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-notice \
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-line \
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+lint=all,noVCDE,noONGS,noUI \
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-timescale=1ns/1ps \
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-quiet \
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-q \
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+rad \
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+vcs+lic+wait \
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+vc+list \
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-error=noZMMCM \
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-error=PCWM-L \
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-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
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+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
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+incdir+$(build_dir) \
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$(PREPROC_DEFINES) \
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-f $(sim_common_files) \
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$(sim_vsrcs)
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#----------------------------------------------------------------------------------------
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# gcc configuration/optimization
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#----------------------------------------------------------------------------------------
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# -flto slows down compilation on small-memory and breaks on firesim-manager
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CMODE := -O3 -fbranch-probabilities -march=native
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VCS_CXXFLAGS = \
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$(CXXFLAGS) \
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$(CMODE) \
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-I$(VCS_HOME)/include \
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-I$(RISCV)/include \
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-I$(dramsim_dir) \
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-std=c++11 \
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$(EXTRA_SIM_CXXFLAGS)
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VCS_LDFLAGS = \
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$(LDFLAGS) \
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$(CMODE) \
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-L$(RISCV)/lib \
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-Wl,-rpath,$(RISCV)/lib \
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-L$(sim_dir) \
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-L$(dramsim_dir) \
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-lfesvr \
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-ldramsim \
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$(EXTRA_SIM_LDFLAGS)
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VCS_CC_OPTS = \
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-CFLAGS "$(VCS_CXXFLAGS)" \
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-LDFLAGS "$(VCS_LDFLAGS)"
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#----------------------------------------------------------------------------------------
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# full vcs+gcc opts
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#----------------------------------------------------------------------------------------
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VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
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#########################################################################################
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# vcs simulator rules
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#########################################################################################
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$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@
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rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \
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-debug_pp
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$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
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+define+DEBUG
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rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \
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+define+DEBUG \
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-debug_pp
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#########################################################################################
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# create a vcs vpd rule
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@@ -60,9 +138,26 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
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$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
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$(output_dir)/none.vpd: $(sim_debug)
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mkdir -p $(output_dir)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log)
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#########################################################################################
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# general cleanup rule
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# general cleanup rules
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#########################################################################################
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.PHONY: clean
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.PHONY: clean clean-sim clean-sim-debug
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clean:
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rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
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rm -rf $(gen_dir) $(sim_prefix)-*
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clean-sim:
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rm -rf csrc/ $(sim) ucli.key vc_hdrs.h
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clean-sim-debug:
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rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h
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#########################################################################################
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# print help text
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#########################################################################################
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.PHONY: help
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help:
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@for line in $(HELP_LINES); do echo "$$line"; done
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@@ -22,7 +22,7 @@ include $(base_dir)/variables.mk
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sim_name = verilator
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#########################################################################################
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# vcs simulator types and rules
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# verilator simulator types and rules
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#########################################################################################
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sim_prefix = simulator
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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@@ -47,67 +47,141 @@ debug: $(sim_debug)
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include $(base_dir)/common.mk
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#########################################################################################
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# verilator binary and flags
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# verilator-specific user-interface variables and commands
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#########################################################################################
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HELP_COMPILATION_VARIABLES += \
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" VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \
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" 'all' if full verilator runtime profiling" \
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" 'threads' if runtime thread profiling only" \
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" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build"
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HELP_COMMANDS += \
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" default = compiles non-debug simulator [./$(shell basename $(sim))]" \
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" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \
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" clean = remove all debug/non-debug simulators and intermediate files" \
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" clean-sim = removes non-debug simulator and verilator-generated files" \
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" clean-sim-debug = removes debug simulator and verilator-generated files"
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#########################################################################################
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# verilator/cxx binary and flags
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#########################################################################################
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VERILATOR := verilator --cc --exe
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CXXFLAGS := \
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$(CXXFLAGS) -O1 -std=c++11 \
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-I$(RISCV)/include \
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-I$(dramsim_dir) \
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-D__STDC_FORMAT_MACROS \
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$(EXTRA_SIM_CC_FLAGS)
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#----------------------------------------------------------------------------------------
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# user configs
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#----------------------------------------------------------------------------------------
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VERILATOR_PROFILE ?= none
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RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,)
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RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
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--prof-threads --prof-cfuncs,\
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$(if $(filter $(VERILATOR_PROFILE),threads),\
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--prof-threads,))
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LDFLAGS := \
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$(LDFLAGS) \
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-L$(sim_dir) \
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-lpthread
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VERILATOR_FST_MODE ?= 0
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TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
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--trace,--trace-fst --trace-threads 1)
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TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
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VERILATOR_CC_OPTS = \
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#----------------------------------------------------------------------------------------
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# verilation configuration/optimization
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#----------------------------------------------------------------------------------------
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# we initially had --noassert for performance, but several modules use
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# assertions, including dramsim, so we enable --assert by default
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VMODE := \
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-O3 \
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-CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \
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-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \
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-LDFLAGS "$(LDFLAGS)" \
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$(RISCV)/lib/libfesvr.a \
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$(dramsim_lib)
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--x-assign fast \
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--x-initial fast \
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--assert \
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--output-split 10000 \
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--output-split-cfuncs 10000
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# default flags added for ariane
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ARIANE_VERILATOR_FLAGS = \
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# default flags added for ariane (-Wno-fatal needed for -Wall to not cause
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# a crash, since 1000s of warnings are generated)
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VERILOG_IP_VERILATOR_FLAGS := \
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--unroll-count 256 \
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-Werror-PINMISSING \
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-Werror-IMPLICIT \
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-Wno-PINCONNECTEMPTY \
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-Wno-ASSIGNDLY \
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-Wno-DECLFILENAME \
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-Wno-UNUSED \
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-Wno-UNOPTFLAT \
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-Wno-BLKANDNBLK \
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-Wno-style \
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-Wall
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-Wno-fatal
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# normal flags used for chipyard builds (that are incompatible with ariane)
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CHIPYARD_VERILATOR_FLAGS = \
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--assert
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# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane)
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CHIPYARD_VERILATOR_FLAGS :=
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# options dependent on whether ariane/NVDLA or chipyard is used
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# NOTE: defer the evaluation of this until it is used!
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PLATFORM_OPTS = $(shell \
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if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
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then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
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else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
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# Use --timescale to approximate timescale behavior of pre-4.034
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TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
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VERILATOR_NONCC_OPTS = \
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$(TIMESCALE_OPTS) \
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--top-module $(VLOG_MODEL) \
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--vpi \
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-Wno-fatal \
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$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
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--output-split 10000 \
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--output-split-cfuncs 100 \
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--max-num-width 1048576 \
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-f $(sim_common_files) \
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$(sim_vsrcs)
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VERILATOR_DEFINES = \
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# see: https://github.com/ucb-bar/riscv-mini/issues/31
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MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
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PREPROC_DEFINES := \
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+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
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+define+STOP_COND=\$$c\(\"done_reset\"\)
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VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES)
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VERILATOR_NONCC_OPTS = \
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$(RUNTIME_PROFILING_VFLAGS) \
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$(VMODE) \
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$(PLATFORM_OPTS) \
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$(TIMESCALE_OPTS) \
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$(MAX_WIDTH_OPTS) \
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$(PREPROC_DEFINES) \
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--top-module $(VLOG_MODEL) \
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--vpi \
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-f $(sim_common_files) \
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$(sim_vsrcs)
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#----------------------------------------------------------------------------------------
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# gcc configuration/optimization
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#----------------------------------------------------------------------------------------
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# -flto slows down compilation on small-memory and breaks on firesim-manager
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CMODE := -O3 -fbranch-probabilities -march=native
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VERILATOR_CXXFLAGS = \
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$(CXXFLAGS) \
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$(RUNTIME_PROFILING_CFLAGS) \
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$(TRACING_CFLAGS) \
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$(CMODE) \
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-std=c++11 \
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-D__STDC_FORMAT_MACROS \
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-DTEST_HARNESS=V$(VLOG_MODEL) \
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-DVERILATOR \
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-I$(RISCV)/include \
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-I$(dramsim_dir) \
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-I$(build_dir) \
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-include $(build_dir)/$(long_name).plusArgs \
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-include $(build_dir)/verilator.h \
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$(EXTRA_SIM_CXXFLAGS)
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VERILATOR_LDFLAGS = \
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$(LDFLAGS) \
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$(RUNTIME_PROFILING_CFLAGS) \
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$(CMODE) \
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-L$(RISCV)/lib \
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-Wl,-rpath,$(RISCV)/lib \
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-L$(sim_dir) \
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-L$(dramsim_dir) \
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-lfesvr \
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-lpthread \
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-ldramsim \
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$(EXTRA_SIM_LDFLAGS)
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VERILATOR_CC_OPTS = \
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-CFLAGS "$(VERILATOR_CXXFLAGS)" \
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-LDFLAGS "$(VERILATOR_LDFLAGS)"
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#----------------------------------------------------------------------------------------
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# full verilator+gcc opts
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#----------------------------------------------------------------------------------------
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VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
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#########################################################################################
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# verilator build paths and file names
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@@ -127,13 +201,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
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$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
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rm -rf $(model_dir)
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mkdir -p $(model_dir)
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$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
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$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
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touch $@
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$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
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rm -rf $(model_dir_debug)
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mkdir -p $(model_dir_debug)
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$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
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$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
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touch $@
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#########################################################################################
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@@ -155,8 +229,21 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
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#########################################################################################
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# general cleanup rule
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# general cleanup rules
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#########################################################################################
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.PHONY: clean
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.PHONY: clean clean-sim clean-sim-debug
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clean:
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rm -rf $(gen_dir) $(sim_prefix)-*
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clean-sim:
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rm -rf $(model_dir) $(sim)
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clean-sim-debug:
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rm -rf $(model_dir_debug) $(sim_debug)
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#########################################################################################
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# print help text
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#########################################################################################
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.PHONY: help
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help:
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@for line in $(HELP_LINES); do echo "$$line"; done
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