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Merge pull request #284 from ucb-bar/add-hwacha-tests

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Check and add Hwacha tests
This commit is contained in:
Abraham Gonzalez
2019-10-14 13:43:24 -04:00
committed by GitHub
parent 7150f509b7 8af172c313
commit b004ecc8bf
2 changed files with 18 additions and 2 deletions
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2
.circleci/defaults.sh
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@@ -46,7 +46,7 @@ mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=LargeBoomAndRocketConfi
mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig"
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"

18
generators/example/src/main/scala/Generator.scala
View File

@@ -1,10 +1,14 @@
package example package example
import scala.util.Try
import chisel3._ import chisel3._
import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.util.{GeneratorApp}
import utilities.TestSuiteHelper import freechips.rocketchip.system.{TestGeneration}
import utilities.{TestSuiteHelper}
object Generator extends GeneratorApp { object Generator extends GeneratorApp {
// add unique test suites // add unique test suites
@@ -12,6 +16,18 @@ object Generator extends GeneratorApp {
implicit val p: Parameters = params implicit val p: Parameters = params
TestSuiteHelper.addRocketTestSuites TestSuiteHelper.addRocketTestSuites
TestSuiteHelper.addBoomTestSuites TestSuiteHelper.addBoomTestSuites
// if hwacha parameter exists then generate its tests
// TODO: find a more elegant way to do this. either through
// trying to disambiguate BuildRoCC, having a AccelParamsKey,
// or having the Accelerator/Tile add its own tests
import hwacha.HwachaTestSuites._
if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
TestGeneration.addSuites(rv64uv.map(_("p")))
TestGeneration.addSuites(rv64uv.map(_("vp")))
TestGeneration.addSuite(rv64sv("p"))
TestGeneration.addSuite(hwachaBmarks)
}
} }
// specify the name that the generator outputs files as // specify the name that the generator outputs files as