From affbdc254b4ee3371c50042167a63d596d77dc85 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 17 Sep 2023 10:33:42 -0700 Subject: [PATCH] Update docs/Simulation/Software-RTL-Simulation.rst --- docs/Simulation/Software-RTL-Simulation.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 86d8a07c..351fdb64 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -177,7 +177,7 @@ A special target that automatically generates the waveform file for a specific t For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. An open-source vcd-capable waveform viewer is `GTKWave `__. -For a VCS simulation, this will generate an fsdb file (fast signal database, a proprietary waveform representation format developed by Novas Software, later acquired by Synopsys) that can be loaded to fsdb-supported waveform viewers. +For a VCS simulation, this will generate an fsdb file that can be loaded to fsdb-supported waveform viewers. If you have Synopsys licenses, we recommend using the Verdi waveform viewer. Visualizing Chipyard SoCs