diff --git a/.gitmodules b/.gitmodules
index b4beb696..f5055865 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -73,9 +73,6 @@
 [submodule "fpga/fpga-shells"]
 	path = fpga/fpga-shells
 	url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
-[submodule "tools/api-config-chipsalliance"]
-	path = tools/api-config-chipsalliance
-	url = https://github.com/chipsalliance/api-config-chipsalliance.git
 [submodule "tools/rocket-dsp-utils"]
 	path = tools/rocket-dsp-utils
 	url = https://github.com/ucb-bar/rocket-dsp-utils
@@ -121,3 +118,6 @@
 [submodule "generators/mempress"]
 	path = generators/mempress
 	url = https://github.com/ucb-bar/mempress.git
+[submodule "tools/cde"]
+	path = tools/cde
+	url = https://github.com/chipsalliance/cde.git
diff --git a/build.sbt b/build.sbt
index 4e9656bc..8160a4f9 100644
--- a/build.sbt
+++ b/build.sbt
@@ -62,7 +62,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.5.5"
+val chiselVersion = "3.5.6"
 
 lazy val chiselSettings = Seq(
   libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
@@ -102,18 +102,8 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
     )
   )
 
-lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
-  .settings(commonSettings)
-  .settings(
-    libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
-    )
-  )
-
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .dependsOn(hardfloat, rocketMacros, rocketConfig)
+  .dependsOn(hardfloat, rocketMacros, cde)
   .settings(commonSettings)
   .settings(chiselSettings)
   .settings(
@@ -251,16 +241,12 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
       "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
   ))
 
-lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance"))
-  .settings(
-    commonSettings,
-    libraryDependencies ++= Seq(
-      "org.scalatest" %% "scalatest" % "3.0.+" % "test",
-      "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
-    ))
+lazy val cde = (project in file("tools/cde"))
+  .settings(commonSettings)
+  .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip")
 
 lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
-  .dependsOn(rocketchip, `api-config-chipsalliance`, dsptools)
+  .dependsOn(rocketchip, cde, dsptools)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index b6cd1bb7..9f4c6ac5 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9
+Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535
diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index a88848d0..10af0223 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 package chipyard.fpga.arty
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
@@ -17,9 +17,9 @@ import chipyard.{BuildSystem}
 
 // DOC include start: AbstractArty and Rocket
 class WithArtyTweaks extends Config(
+  new WithArtyResetHarnessBinder ++
   new WithArtyJTAGHarnessBinder ++
   new WithArtyUARTHarnessBinder ++
-  new WithArtyResetHarnessBinder ++
   new WithDebugResetPassthrough ++
 
   new chipyard.config.WithDTSTimebase(32768) ++
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 4e90e858..84d47967 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.arty
 
 import chisel3._
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 import freechips.rocketchip.jtag.{JTAGIO}
 
 import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
@@ -15,15 +15,15 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
 import chipyard.iobinders.JTAGChipIO
 
 class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
-  (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
-    require(ports.size == 2)
-
+  (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
+    val resetPorts = ports.collect { case b: Bool => b }
+    require(resetPorts.size == 2)
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       // Debug module reset
-      th.dut_ndreset := ports(0)
+      th.dut_ndreset := resetPorts(0)
 
       // JTAG reset
-      ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
+      resetPorts(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
     }
   }
 })
@@ -63,6 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
         io_jtag.TMS.i.po.map(_ := DontCare)
         io_jtag.TDO.i.po.map(_ := DontCare)
       }
+      case b: Bool =>
     }
   }
 })
diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala
index db656752..da6c7318 100644
--- a/fpga/src/main/scala/arty/IOBinders.scala
+++ b/fpga/src/main/scala/arty/IOBinders.scala
@@ -3,12 +3,12 @@ package chipyard.fpga.arty
 import chisel3._
 import chisel3.experimental.{IO}
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 
 import chipyard.iobinders.{ComposeIOBinder}
 
 class WithDebugResetPassthrough extends ComposeIOBinder({
-  (system: HasPeripheryDebugModuleImp) => {
+  (system: HasPeripheryDebug) => {
     // Debug module reset
     val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
     io_ndreset := system.debug.get.ndreset
diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
index a3d7fc33..5e280469 100644
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty
 import chisel3._
 
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 0930dbdb..673b8b58 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 package chipyard.fpga.arty100t
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 5cc1e348..88ea88af 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty100t
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
 
 import sifive.fpgashells.shell.xilinx._
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 3d86f354..d9a2df45 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -2,7 +2,6 @@ package chipyard.fpga.arty100t
 
 import chisel3._
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 07a96cfd..fa08a184 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vc707
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala
index 924c768e..94c0ba8e 100644
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
 import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index 85b6ee24..c4f4684e 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala
index 250e2040..02669b79 100644
--- a/fpga/src/main/scala/vcu118/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118
 import chisel3._
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
 
 import sifive.fpgashells.shell._
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 9a3cc0d5..e46745a8 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
 import sifive.fpgashells.shell.xilinx._
diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
index 62c2af31..bff715dc 100644
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup
 
 import math.min
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.diplomacy._
diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
index 43d559f0..4b9604f9 100644
--- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{attach}
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
 
 import sifive.fpgashells.shell._
diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
index 5b554f5b..c5401d32 100644
--- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 2406cb7b..c311d84f 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118.bringup
 import chisel3._
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 
diff --git a/generators/boom b/generators/boom
index 051dbadb..1b1f210b 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 051dbadb6d0e9018c5b1f843ac73cff4242a02f8
+Subproject commit 1b1f210bcf5985c1e1f588c1639d5d0ec2d04998
diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
index 184f30f2..150221b6 100644
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer}
 
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import chipyard.iobinders._
diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala
index 7b663b24..fffb97d6 100644
--- a/generators/chipyard/src/main/scala/Cospike.scala
+++ b/generators/chipyard/src/main/scala/Cospike.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IntParam, StringParam, IO}
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.devices.tilelink._
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 2777ba36..d20bade9 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 
 // ------------------------------------
diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
index 21dfe588..1992bc1e 100644
--- a/generators/chipyard/src/main/scala/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
 
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.devices.debug._
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 9ef32091..f883931e 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -3,7 +3,7 @@ package chipyard.iobinders
 import chisel3._
 import chisel3.experimental.{Analog, IO, DataMirror}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.jtag.{JTAGIO}
@@ -248,7 +248,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
     def clockBundle = clockSinkNode.get.in.head._1
 
 
-    InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => {
+    InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
       system.debug.map({ debug =>
         // We never use the PSDIO, so tie it off on-chip
         system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index 98c750ce..9aac7421 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{IntParam, StringParam, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index a2f81c0a..6a07ff64 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -9,9 +9,9 @@ import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.prci._
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey}
 import sifive.blocks.devices.uart.{HasPeripheryUART, PeripheryUARTKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
@@ -71,6 +71,7 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
 
 class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
   with HasTiles
+  with HasPeripheryDebug
   with CanHaveHTIF
   with CanHaveChosenInDTS
 {
diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index 827b97c0..a6c4b6b3 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -7,7 +7,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala
index 240ae5cc..23bda680 100644
--- a/generators/chipyard/src/main/scala/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
 
diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index a47ae425..0e4e3310 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{XLen, TileParams}
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 /**
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
index 07ae536b..c8bad8c4 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
index 965beed3..39cb379b 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Config, Field}
+import org.chipsalliance.cde.config.{Parameters, Config, Field}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 
diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
index d72b2a70..121cca24 100644
--- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
+++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
index 0cfc702a..d2c4f2e5 100644
--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer}
 
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
index 5ca8d271..9b7696fb 100644
--- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
index b67371d5..d8243e37 100644
--- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index c13139bf..c9a6e838 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -1,6 +1,6 @@
 package chipyard.config
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // --------------
 // Chipyard abstract ("base") configuration
diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
index 0de224c9..4c101403 100644
--- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // BOOM Configs
diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala
index 132a3009..c0d6adb1 100644
--- a/generators/chipyard/src/main/scala/config/CVA6Configs.scala
+++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // CVA6 Configs
diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
index 8e8c7fe9..206b086b 100644
--- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // Heterogenous Configs
diff --git a/generators/chipyard/src/main/scala/config/IbexConfigs.scala b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
index 63b7aa5d..6d1b6e4e 100644
--- a/generators/chipyard/src/main/scala/config/IbexConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // Ibex Configs
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index aa04cfe1..6a7710d9 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index bd36fe04..0036e988 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 import freechips.rocketchip.subsystem.{SBUS, MBUS}
 
diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
index 9d0c4132..10be8aca 100644
--- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index d01bcd8d..3bb2390d 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ---------------------------------------------------------
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index 7487a50e..4077fcbd 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index f70ef274..01d901aa 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
diff --git a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
index 3eb568ba..43ad1de3 100644
--- a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 3679ed07..24eb1f4d 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index cc6d0c90..cb82360e 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -1,7 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.rocket.{DCacheParams}
+import org.chipsalliance.cde.config.{Config}
 
 // Configs which instantiate a Spike-simulated
 // tile that interacts with the Chipyard SoC
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 4ab51994..605db4d3 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.rocket.{DCacheParams}
 
 class AbstractTraceGenConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index c871ba6f..daa08265 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import constellation.channel._
 import constellation.routing._
 import constellation.topology._
diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index 0c79f6dc..7000c81c 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -4,7 +4,7 @@ import scala.util.matching.Regex
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.diplomacy._
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index ec9ff47c..7ac7f569 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -4,7 +4,7 @@ import scala.util.matching.Regex
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
 import freechips.rocketchip.stage.phases.TargetDirKey
diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
index 774b23c2..4680eeeb 100644
--- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
@@ -2,7 +2,7 @@ package chipyard.config
 
 import chisel3._
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.diplomacy._
 
diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
index c41e2716..40f18d5d 100644
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -1,6 +1,6 @@
 package chipyard.config
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
 import freechips.rocketchip.diplomacy.{DTSTimebase}
 
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index f19759cb..56042c3d 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -2,7 +2,7 @@ package chipyard.config
 
 import chisel3._
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
diff --git a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
index 2e849c58..c8b4f828 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
@@ -1,6 +1,6 @@
 package chipyard.config
 
-import freechips.rocketchip.config.{Config, Field, Parameters}
+import org.chipsalliance.cde.config.{Config, Field, Parameters}
 import tracegen.{TraceGenSystem}
 import chipyard.{BuildSystem}
 import chipyard.clocking.{HasChipyardPRCI}
diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
index fe55f288..bf05ba9c 100644
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import chisel3.experimental.{IntParam, BaseModule}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.subsystem.BaseSubsystem
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
 import freechips.rocketchip.tilelink._
diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
index 5051c37d..bb6ecd72 100644
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -3,7 +3,7 @@ package chipyard.example
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import freechips.rocketchip.tilelink._
 
diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala
index cafc470f..1cdddd32 100644
--- a/generators/chipyard/src/main/scala/example/NodeTypes.scala
+++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala
@@ -1,6 +1,6 @@
 package chipyard.example
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
diff --git a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
index cda91ffe..e7a8b0b8 100644
--- a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
+++ b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
@@ -2,7 +2,7 @@
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink.TLRegisterNode
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 3d8e1ae1..1a9114b9 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -3,7 +3,7 @@ package chipyard.example
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
index b51e2223..9ad23a4c 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
 import freechips.rocketchip.amba.axi4stream._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index f45b318c..15dfb992 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
 import freechips.rocketchip.amba.axi4stream._
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
index c6ffaf42..2846277c 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
 import freechips.rocketchip.amba.axi4stream._
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
index 03aa0b56..2258228e 100644
--- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
+++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
@@ -6,7 +6,7 @@ package chipyard.stage.phases
 import scala.util.Try
 import scala.collection.mutable
 
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import chisel3.stage.phases.Elaborate
 import firrtl.AnnotationSeq
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
diff --git a/generators/chipyard/src/main/scala/unittest/TestHarness.scala b/generators/chipyard/src/main/scala/unittest/TestHarness.scala
index 8bb4bbd9..a5ca5551 100644
--- a/generators/chipyard/src/main/scala/unittest/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala
@@ -1,7 +1,7 @@
 package chipyard.unittest
 
 import chisel3._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle { val success = Output(Bool()) })
diff --git a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
index 40e991a2..d3281dc1 100644
--- a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
+++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
@@ -1,6 +1,6 @@
 package chipyard.unittest
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}
 
 class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {
diff --git a/generators/constellation b/generators/constellation
index 4606ee19..e9f1c828 160000
--- a/generators/constellation
+++ b/generators/constellation
@@ -1 +1 @@
-Subproject commit 4606ee19b74d32d165b1708ef6f4ee98baa1c50d
+Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62
diff --git a/generators/cva6 b/generators/cva6
index 737fd83b..0011494b 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 737fd83b820aea6d615f372a97766b1d390a18d5
+Subproject commit 0011494bb70d2327ab4d6b0258f5073f137927ee
diff --git a/generators/fft-generator b/generators/fft-generator
index a31bd038..be8ab768 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit a31bd038ddf3c941634cb830608edb0bdd6442db
+Subproject commit be8ab768bd15824c69531df632478e4429078b94
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 4d64a8ad..4d768da9 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -6,9 +6,9 @@ import chisel3._
 import chisel3.experimental.annotate
 import chisel3.util.experimental.BoringUtils
 
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{RocketTile}
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index bd35341b..a62059e3 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -9,7 +9,7 @@ import chisel3.experimental.{IO}
 
 import freechips.rocketchip.prci._
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
 import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
 
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 2ea848df..7af98c57 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -4,7 +4,7 @@ import java.io.File
 
 import chisel3._
 import chisel3.util.{log2Up}
-import freechips.rocketchip.config.{Parameters, Config}
+import org.chipsalliance.cde.config.{Parameters, Config}
 import freechips.rocketchip.groundtest.TraceGenParams
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
diff --git a/generators/gemmini b/generators/gemmini
index 4dd19f3e..965ea0b3 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit 4dd19f3e93d2decc24048eb1776e53fb20855841
+Subproject commit 965ea0b3c5ffd7b68e6bf5a50ea9ff0750a5b988
diff --git a/generators/hwacha b/generators/hwacha
index e1be8e2a..d01ca1e7 160000
--- a/generators/hwacha
+++ b/generators/hwacha
@@ -1 +1 @@
-Subproject commit e1be8e2a41c6bc2239aed4e23355cf34a224f380
+Subproject commit d01ca1e7f8a3ba3f419509273dfef00e41095f6a
diff --git a/generators/ibex b/generators/ibex
index 626127f2..916fb7a6 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 626127f229dd6dc926b7670eb4dd138f32a7940a
+Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c
diff --git a/generators/icenet b/generators/icenet
index 90d52a6a..ce1ec55c 160000
--- a/generators/icenet
+++ b/generators/icenet
@@ -1 +1 @@
-Subproject commit 90d52a6a8435c862e6435d04436f587c3b36c8c0
+Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20
diff --git a/generators/mempress b/generators/mempress
index b9eaedc0..295ae085 160000
--- a/generators/mempress
+++ b/generators/mempress
@@ -1 +1 @@
-Subproject commit b9eaedc061adbbe488f4c094f0ddd2177852e11a
+Subproject commit 295ae0854a429182e4a38b120c8771a4e898834e
diff --git a/generators/nvdla b/generators/nvdla
index 2b17011b..7130a5c0 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d
+Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index d6ccc5de..c051956d 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit d6ccc5de5cf6f07be500a0d1351656bb0c50e4a3
+Subproject commit c051956d3be3269c4ed9fcbb6afe920a6f54fd32
diff --git a/generators/rocket-chip b/generators/rocket-chip
index f5ebf26b..25e2c635 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit f5ebf26b369922b2924d71e185c473c0385bf54e
+Subproject commit 25e2c63567689ebe1fc5e60fdfe3375a8dba071c
diff --git a/generators/sha3 b/generators/sha3
index 8c5d2443..1fa5ef8a 160000
--- a/generators/sha3
+++ b/generators/sha3
@@ -1 +1 @@
-Subproject commit 8c5d244303694311c4e63e51915a492491a3f5c7
+Subproject commit 1fa5ef8ae5b67126d709193896e75dba50c5fd28
diff --git a/generators/sifive-blocks b/generators/sifive-blocks
index 3938f301..534d3b74 160000
--- a/generators/sifive-blocks
+++ b/generators/sifive-blocks
@@ -1 +1 @@
-Subproject commit 3938f301ce453c86e908211788017fd3a7e2765e
+Subproject commit 534d3b74a0f22e67198aa361ae987042ee56dead
diff --git a/generators/sifive-cache b/generators/sifive-cache
index 850e1215..02e002b3 160000
--- a/generators/sifive-cache
+++ b/generators/sifive-cache
@@ -1 +1 @@
-Subproject commit 850e12154c1de6baee9e40094d115e9b85d799b1
+Subproject commit 02e002b324c0e6316234045fa739fdb9d716170d
diff --git a/generators/testchipip b/generators/testchipip
index dead693f..ee47d2ea 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31
+Subproject commit ee47d2ea205c7525b21333d3caf835fcd963fa42
diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
index ac2477a1..5d4f0211 100644
--- a/generators/tracegen/src/main/scala/Configs.scala
+++ b/generators/tracegen/src/main/scala/Configs.scala
@@ -2,7 +2,7 @@ package tracegen
 
 import chisel3._
 import chisel3.util.log2Ceil
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index fceb0072..2a0ba3d5 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -1,9 +1,9 @@
 package tracegen
 
 import chisel3._
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
-import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
+import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
 import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
 import freechips.rocketchip.subsystem._
 import boom.lsu.BoomTraceGenTile
@@ -17,6 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     case t: GroundTestTile => t.statusNode.makeSink()
     case t: BoomTraceGenTile => t.statusNode.makeSink()
   }
+  lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
   override lazy val module = new TraceGenSystemModuleImp(this)
 }
 
diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh
index 9c6d0389..0ecdbb27 100755
--- a/scripts/repo-clean.sh
+++ b/scripts/repo-clean.sh
@@ -21,7 +21,7 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
     popd
 )
 (
-    pushd $RDIR/tools/api-config-chipsalliance
+    pushd $RDIR/tools/cde
     git config --local status.showUntrackedFiles no
     popd
 )
diff --git a/sims/firesim b/sims/firesim
index 68e51138..8c85960b 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 68e5113887d36e87bb6202e7fd1e7e51e786a91b
+Subproject commit 8c85960b939a0090de30a31936981972874d979d
diff --git a/tools/api-config-chipsalliance b/tools/api-config-chipsalliance
deleted file mode 160000
index fd8df110..00000000
--- a/tools/api-config-chipsalliance
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4
diff --git a/tools/cde b/tools/cde
new file mode 160000
index 00000000..384c06b8
--- /dev/null
+++ b/tools/cde
@@ -0,0 +1 @@
+Subproject commit 384c06b8d45c8184ca2f3fba2f8e78f79d2c1b51
diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils
index 46d6ed77..dcd9eb21 160000
--- a/tools/rocket-dsp-utils
+++ b/tools/rocket-dsp-utils
@@ -1 +1 @@
-Subproject commit 46d6ed77981ef18789636426cc23f0bd7edc64d9
+Subproject commit dcd9eb212aefd8040cdf9c50adffbbf975422a1d