From af0dce8e8a9f4c249bb93710fe329afebb0f5dbe Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 24 May 2023 18:39:08 -0700 Subject: [PATCH] Switch to PeripheryUARTTSI --- .../chipyard/src/main/scala/DigitalTop.scala | 1 + .../chipyard/src/main/scala/IOBinders.scala | 9 +++++++++ .../main/scala/config/AbstractConfig.scala | 20 +++++++++++-------- .../config/PeripheralDeviceConfigs.scala | 10 ++++++++++ .../src/main/scala/config/RocketConfigs.scala | 8 -------- .../main/scala/harness/HarnessBinders.scala | 19 ++++++------------ 6 files changed, 38 insertions(+), 29 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 6711eac7..c7099f97 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem + with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 8dd0020e..11dff842 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -411,6 +411,15 @@ class WithCustomBootPin extends OverrideIOBinder({ }).getOrElse((Nil, Nil)) }) +class WithUARTTSIPunchthrough extends OverrideIOBinder({ + (system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p => + val sys = system.asInstanceOf[BaseSubsystem] + val port = IO(new UARTPortIO(p.c)) + port <> p + (Seq(port), Nil) + }).getOrElse((Nil, Nil)) +}) + class WithTLMemPunchthrough extends OverrideIOBinder({ (system: CanHaveMasterTLMemPort) => { val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave") diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 48f10cd9..063b21d4 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -22,25 +22,29 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present + new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port new chipyard.harness.WithClockAndResetFromHarness ++ // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz // The IOBinders instantiate ChipTop IOs to match desired digital IOs - // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through + // IOCells are generated for "Chip-like" IOs + new chipyard.iobinders.WithSerialTLIOCells ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ + new chipyard.iobinders.WithGPIOCells ++ + new chipyard.iobinders.WithSPIIOCells ++ + new chipyard.iobinders.WithExtInterruptIOCells ++ + new chipyard.iobinders.WithCustomBootPin ++ + // The "punchtrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO + // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ new chipyard.iobinders.WithTLMemPunchthrough ++ new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++ new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++ new chipyard.iobinders.WithNICIOPunchthrough ++ - new chipyard.iobinders.WithSerialTLIOCells ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ - new chipyard.iobinders.WithGPIOCells ++ - new chipyard.iobinders.WithSPIIOCells ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ - new chipyard.iobinders.WithExtInterruptIOCells ++ - new chipyard.iobinders.WithCustomBootPin ++ + new chipyard.iobinders.WithUARTTSIPunchthrough ++ // By default, punch out IOs to the Harness new chipyard.clocking.WithPassthroughClockGenerator ++ diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 8da229b4..9eec165e 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -80,3 +80,13 @@ class QuadChannelRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) + +class UARTTSIRocketConfig extends Config( + new chipyard.harness.WithSerialTLTiedOff ++ + new testchipip.WithUARTTSIClient ++ + new chipyard.config.WithMemoryBusFrequency(10) ++ + new chipyard.config.WithFrontBusFrequency(10) ++ + new chipyard.config.WithPeripheryBusFrequency(10) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new chipyard.config.AbstractConfig) + diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index af6bfc1d..2bcc0089 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -19,14 +19,6 @@ class TinyRocketConfig extends Config( new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new chipyard.config.AbstractConfig) -class UARTTSIRocketConfig extends Config( - new chipyard.harness.WithUARTSerial ++ - new chipyard.config.WithNoUART ++ - new chipyard.config.WithMemoryBusFrequency(10) ++ - new chipyard.config.WithPeripheryBusFrequency(10) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new chipyard.config.AbstractConfig) - class SimAXIRocketConfig extends Config( new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index a78c748b..69d6f6d3 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -317,21 +317,14 @@ class WithSimTSIOverSerialTL extends OverrideHarnessBinder({ } }) -class WithUARTSerial extends OverrideHarnessBinder({ - (system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => { +class WithSimUARTToUARTTSI extends OverrideHarnessBinder({ + (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTPortIO]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val freq = p(PeripheryBusKey).dtsFrequency.get - val bits = port.bits - port.clock := th.harnessBinderClock - val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset) - val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0))) - val serial_width_adapter = Module(new SerialWidthAdapter( - 8, TSI.WIDTH)) - ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide) - UARTAdapter.connect(Seq(uart_to_serial.io.uart), uart_to_serial.div) - serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial) - th.success := false.B + UARTAdapter.connect(Seq(port), + baudrate=port.c.initBaudRate, + clockFrequency=th.getHarnessBinderClockFreqHz.toInt, + forcePty=true) }) } })