wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Incorporate feedback

Browse Source
This commit is contained in:
Paul Rigge
2020-05-25 20:23:19 +00:00
parent f56e367d59
commit ae1aa31fce
5 changed files with 68 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -23,8 +23,8 @@ class DigitalTop(implicit p: Parameters) extends System
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget
with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget
with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
{
override lazy val module = new DigitalTopModule(this)

44
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -426,16 +426,44 @@ class RingSystemBusRocketConfig extends Config(
new freechips.rocketchip.system.BaseConfig)
// DOC include end: RingSystemBusRocket
class UIntStreamingPassthroughRocketConfig extends Config(
new chipyard.example.WithUIntStreamingPassthrough ++ // use top with tilelink-controlled passthrough
new RocketConfig
)
class StreamingPassthroughRocketConfig extends Config(
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
// DOC include start: FIRRocketConfig
class UIntTestFIRRocketConfig extends Config (
new chipyard.example.WithUIntTestFIR ++ // use top with tilelink-controlled FIR
new RocketConfig
)
class FIRRocketConfig extends Config (
new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
// DOC include end: FIRRocketConfig
class SmallNVDLARocketConfig extends Config(

12
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
View File

@@ -200,8 +200,8 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para
}
// DOC include end: TLGenericFIRChain chisel
// DOC include start: CanHavePeripheryUIntTestFIR chisel
trait CanHavePeripheryUIntTestFIR extends BaseSubsystem {
// DOC include start: CanHavePeripheryFIR chisel
trait CanHavePeripheryFIR extends BaseSubsystem {
val fir = p(GenericFIRKey) match {
case Some(params) => {
val fir = LazyModule(new TLGenericFIRChain(
@@ -216,13 +216,13 @@ trait CanHavePeripheryUIntTestFIR extends BaseSubsystem {
case None => None
}
}
// DOC include end: CanHavePeripheryUIntTestFIR chisel
// DOC include end: CanHavePeripheryFIR chisel
/**
* Mixin to add FIR to rocket config
*/
// DOC include start: WithTestFIR
class WithUIntTestFIR extends Config((site, here, up) => {
// DOC include start: WithFIR
class WithFIR extends Config((site, here, up) => {
case GenericFIRKey => Some(GenericFIRParams(depth = 8))
})
// DOC include end: WithTestFIR
// DOC include end: WithFIR

4
generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala → generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
View File

@@ -133,7 +133,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
lazy val module = new LazyModuleImp(this)
}
trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem =>
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => {
val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
@@ -150,7 +150,7 @@ trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem =>
/**
* Mixin to add passthrough to rocket config
*/
class WithUIntStreamingPassthrough extends Config((site, here, up) => {
class WithStreamingPassthrough extends Config((site, here, up) => {
case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8))
})