Closer [ci skip]
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11
common.mk
11
common.mk
@@ -126,7 +126,7 @@ firrtl: $(FIRRTL_FILE)
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#########################################################################################
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# create verilog files rules and variables
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#########################################################################################
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CIRCT_TARGETS = $(VSRC_SMEMS_FILE) $(VSRC_MODH_JSON)
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CIRCT_TARGETS = $(VSRC_SMEMS_CONF) $(VSRC_MODH_JSON)
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# DOC include start: FirrtlCompiler
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$(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
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@@ -170,14 +170,17 @@ firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
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--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
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--repl-seq-mem \
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--repl-seq-mem-circuit=$(MODEL) \
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--repl-seq-mem-file=$(VSRC_SMEMS_FILE) \
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--repl-seq-mem-file=$(VSRC_SMEMS_CONF) \
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--split-verilog \
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-o $(VSRC_DUMP) \
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$(FIRRTL_FILE)
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# touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
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>>>>>>> 9306c549 (Initial CIRCT integration [ci skip])
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# DOC include end: FirrtlCompiler
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$(TOP_MODS_FILE) $(HARNESS_MODS_FILE): $(VSRC_MODH_JSON)
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$(base_dir)/scripts/dump-mods.py $(TOP) $^ > $(TOP_MODS_FILE)
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$(base_dir)/scripts/dump-mods.py $(MODEL) $^ > $(HARNESS_MODS_FILE)
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# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
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MACROCOMPILER_MODE ?= --mode synflops
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$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
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@@ -190,7 +193,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEM
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########################################################################################
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# remove duplicate files and headers in list of simulation file inputs
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########################################################################################
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$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
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$(sim_common_files): $(sim_files)
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sort -u $^ | grep -v '.*\.\(svh\|h\)$$' > $@
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#########################################################################################
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