Adding support for Scala 2.13

Mostly import changes
Some formatting changes
Runs +test
This commit is contained in:
chick
2021-08-16 10:15:07 -07:00
parent b2cee7ccb8
commit ae01e170db
6 changed files with 26 additions and 22 deletions

View File

@@ -14,7 +14,7 @@ import firrtl.ir._
import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation}
import firrtl.transforms.NoDCEAnnotation
import firrtl.{PrimOps, _}
import mdf.macrolib._
import mdf.macrolib.{PolarizedPort, PortPolarity, SRAMCompiler, SRAMGroup, SRAMMacro}
import java.io.{File, FileWriter}
import scala.collection.mutable.{ArrayBuffer, HashMap}
@@ -109,15 +109,16 @@ object MacroCompilerAnnotation {
* @param forceSynflops Set of memories to force compiling as flops regardless of the mode
*/
case class Params(
mem: String,
memFormat: Option[String],
lib: Option[String],
hammerIR: Option[String],
costMetric: CostMetric,
mode: CompilerMode,
useCompiler: Boolean,
forceCompile: Set[String],
forceSynflops: Set[String])
mem: String,
memFormat: Option[String],
lib: Option[String],
hammerIR: Option[String],
costMetric: CostMetric,
mode: CompilerMode,
useCompiler: Boolean,
forceCompile: Set[String],
forceSynflops: Set[String]
) extends Serializable
/** Create a MacroCompilerAnnotation.
* @param c Top-level circuit name (see class description)
@@ -721,16 +722,16 @@ class MacroCompilerTransform extends Transform with DependencyAPIMigration {
// Read, eliminate None, get only SRAM, make firrtl macro
val mems: Option[Seq[Macro]] = (memFileFormat match {
case Some("conf") => Utils.readConfFromPath(Some(memFile))
case Some("conf") => readConfFromPath(Some(memFile))
case _ => mdf.macrolib.Utils.readMDFFromPath(Some(memFile))
}) match {
case Some(x: Seq[mdf.macrolib.Macro]) =>
Some(Utils.filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
Some(filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
case _ => None
}
val libs: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
case Some(x: Seq[mdf.macrolib.Macro]) =>
Some(Utils.filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
Some(filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
case _ => None
}
val compilers: Option[mdf.macrolib.SRAMCompiler] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
@@ -866,10 +867,9 @@ object MacroCompiler extends App {
try {
val macros = params.get(MacrosFormat) match {
case Some("conf") =>
Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox)
filterForSRAM(readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox)
case _ =>
Utils
.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros)))
filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros)))
.get
.map(x => (new Macro(x)).blackbox)
}

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@@ -54,13 +54,13 @@ object FlipChipMacro {
val bumpDimensions: (Int, Int) = json.get("bump_dimensions") match {
case Some(JsArray(x)) if x.size == 2 =>
val z = x.map(_.as[JsNumber].value.intValue())
val z = x.map(_.as[JsNumber].value.intValue)
(z(0), z(1))
case None => return None
}
val bumpLocations: Seq[Seq[String]] = json.get("bump_locations") match {
case Some(JsArray(array)) =>
array.collect { case JsArray(a2) => a2.map(_.toString) }
array.collect { case JsArray(a2) => a2.map(_.toString).toSeq }.toSeq
case _ => return None
}
// Can't have dimensions and locations which don't match

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@@ -1,6 +1,7 @@
package barstools.macros
import mdf.macrolib._
import mdf.macrolib.SRAMMacro
/** Tests to check that the cost function mechanism is working properly. */