Adding support for Scala 2.13
Mostly import changes Some formatting changes Runs +test
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@@ -14,7 +14,7 @@ import firrtl.ir._
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import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, OutputFileAnnotation, RunFirrtlTransformAnnotation}
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import firrtl.transforms.NoDCEAnnotation
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import firrtl.{PrimOps, _}
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import mdf.macrolib._
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import mdf.macrolib.{PolarizedPort, PortPolarity, SRAMCompiler, SRAMGroup, SRAMMacro}
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import java.io.{File, FileWriter}
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import scala.collection.mutable.{ArrayBuffer, HashMap}
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@@ -109,15 +109,16 @@ object MacroCompilerAnnotation {
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* @param forceSynflops Set of memories to force compiling as flops regardless of the mode
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*/
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case class Params(
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mem: String,
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memFormat: Option[String],
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lib: Option[String],
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hammerIR: Option[String],
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costMetric: CostMetric,
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mode: CompilerMode,
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useCompiler: Boolean,
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forceCompile: Set[String],
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forceSynflops: Set[String])
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mem: String,
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memFormat: Option[String],
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lib: Option[String],
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hammerIR: Option[String],
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costMetric: CostMetric,
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mode: CompilerMode,
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useCompiler: Boolean,
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forceCompile: Set[String],
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forceSynflops: Set[String]
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) extends Serializable
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/** Create a MacroCompilerAnnotation.
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* @param c Top-level circuit name (see class description)
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@@ -721,16 +722,16 @@ class MacroCompilerTransform extends Transform with DependencyAPIMigration {
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// Read, eliminate None, get only SRAM, make firrtl macro
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val mems: Option[Seq[Macro]] = (memFileFormat match {
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case Some("conf") => Utils.readConfFromPath(Some(memFile))
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case Some("conf") => readConfFromPath(Some(memFile))
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case _ => mdf.macrolib.Utils.readMDFFromPath(Some(memFile))
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}) match {
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case Some(x: Seq[mdf.macrolib.Macro]) =>
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Some(Utils.filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
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Some(filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
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case _ => None
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}
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val libs: Option[Seq[Macro]] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
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case Some(x: Seq[mdf.macrolib.Macro]) =>
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Some(Utils.filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
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Some(filterForSRAM(Some(x)).getOrElse(List()).map { new Macro(_) })
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case _ => None
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}
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val compilers: Option[mdf.macrolib.SRAMCompiler] = mdf.macrolib.Utils.readMDFFromPath(libFile) match {
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@@ -866,10 +867,9 @@ object MacroCompiler extends App {
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try {
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val macros = params.get(MacrosFormat) match {
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case Some("conf") =>
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Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox)
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filterForSRAM(readConfFromPath(params.get(Macros))).get.map(x => (new Macro(x)).blackbox)
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case _ =>
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Utils
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.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros)))
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filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros)))
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.get
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.map(x => (new Macro(x)).blackbox)
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}
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@@ -54,13 +54,13 @@ object FlipChipMacro {
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val bumpDimensions: (Int, Int) = json.get("bump_dimensions") match {
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case Some(JsArray(x)) if x.size == 2 =>
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val z = x.map(_.as[JsNumber].value.intValue())
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val z = x.map(_.as[JsNumber].value.intValue)
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(z(0), z(1))
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case None => return None
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}
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val bumpLocations: Seq[Seq[String]] = json.get("bump_locations") match {
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case Some(JsArray(array)) =>
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array.collect { case JsArray(a2) => a2.map(_.toString) }
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array.collect { case JsArray(a2) => a2.map(_.toString).toSeq }.toSeq
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case _ => return None
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}
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// Can't have dimensions and locations which don't match
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@@ -1,6 +1,7 @@
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package barstools.macros
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import mdf.macrolib._
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import mdf.macrolib.SRAMMacro
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/** Tests to check that the cost function mechanism is working properly. */
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