wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins

Browse Source
This commit is contained in:
abejgonzalez
2019-04-17 23:11:14 -07:00
parent e71bf2139f
commit adb8897e35
3 changed files with 40 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
common.mk
View File

@@ -20,12 +20,13 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class
#########################################################################################
# jar creation variables and rules
#########################################################################################
FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
FIRRTL_DIR = $(base_dir)/tools/firrtl
FIRRTL_JAR ?= $(base_dir)/lib/firrtl.jar
$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
$(FIRRTL_JAR): $(call lookup_scala_srcs, $(FIRRTL_DIR)/firrtl/src/main/scala)
$(MAKE) -C $(FIRRTL_DIR) SBT="$(SBT)" root_dir=$(FIRRTL_DIR) build-scala
mkdir -p $(dir $@)
cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
cp -p $(FIRRTL_DIR)/utils/bin/firrtl.jar $@
touch $@
#########################################################################################
@@ -49,7 +50,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -ll info -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)