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fix docs bugs

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alonamid
2019-09-25 19:42:18 -07:00
parent 7420841f24
commit adaebd30b9
1 changed files with 2 additions and 3 deletions
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5
docs/Simulation/Software-RTL-Simulation.rst
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@@ -27,6 +27,7 @@ Choice of Simulator
First, we will start by entering the Verilator or VCS directory: First, we will start by entering the Verilator or VCS directory:
For an open-source Verilator simulation, enter the ``sims/verilator`` directory For an open-source Verilator simulation, enter the ``sims/verilator`` directory
.. code-block:: shell .. code-block:: shell
# Enter Verilator directory # Enter Verilator directory
@@ -86,9 +87,7 @@ Each of these make variables correspond to a particular part of the design/codeb
The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build. The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build.
The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class. The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class.