[clocks] Remove dealiaser and node injector until they are needed

generators/chipyard/src/main/scala/Clocks.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider}
 
 import barstools.iocell.chisel._
 
-import chipyard.clocking.{IdealizedPLL, ClockGroupDealiaser, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
+import chipyard.clocking.{IdealizedPLL, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
 
 /**
   * Chipyard provides three baseline, top-level reset schemes, set using the

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -31,8 +31,6 @@ import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingScheme
 // Imports for multiclock sketch
 import boom.common.{BoomTile, BoomTileParams}
 import ariane.{ArianeTile, ArianeTileParams}
-import chipyard.{GenericallyAttachableTile, GenericCrossingParams}
-import chipyard.clocking.{ClockNodeInjectionUtils }
 // -----------------------
 // Common Config Fragments
 // -----------------------
@@ -169,22 +167,6 @@ class WithDMIDTM extends Config((site, here, up) => {
 
 class WithNoDebug extends Config((site, here, up) => {
   case DebugModuleKey => None
+
 })
-
-// Multiclock sketch
-//class WithForcedTileFrequency(fMHz: Double) extends Config((site, here, up) => {
-//  case TilesLocated(InSubsystem) =>
-//    val genericAttachParams = up(TilesLocated(InSubsystem), site) map {
-//      case b: BoomTileAttachParams => GenericallyAttachableTile[BoomTile](
-//        b.tileParams, GenericCrossingParams(b.crossingParams), b.lookup)
-//      case r: RocketTileAttachParams => GenericallyAttachableTile[RocketTile](
-//        r.tileParams, GenericCrossingParams(r.crossingParams), r.lookup)
-//      case a: ArianeTileAttachParams => GenericallyAttachableTile[ArianeTile](
-//        a.tileParams, GenericCrossingParams(a.crossingParams), a.lookup)
-//      case g: GenericallyAttachableTile[_] => g
-//    }
-//   genericAttachParams.map(p => p.copy(crossingParams = p.crossingParams.copy(
-//     injectClockNodeFunc = ClockNodeInjectionUtils.forceTakeFrequency(fMHz))))
-//})
-
 class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)

generators/chipyard/src/main/scala/GenericAttachParams.scala

@@ -1,38 +0,0 @@
-
-package chipyard
-
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{LookupByHartIdImpl, TileParams, InstantiableTileParams, BaseTile}
-
-import chipyard.clocking.ClockNodeInjectionUtils._
-
-case class GenericCrossingParams(
-    crossingType: ClockCrossingType = SynchronousCrossing(),
-    master: TilePortParamsLike = TileMasterPortParams(),
-    slave: TilePortParamsLike = TileSlavePortParams(),
-    mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS,
-    injectClockNodeFunc: InjectClockNodeFunc = injectIdentityClockNode,
-    forceSeparateClockReset: Boolean = false) extends TileCrossingParamsLike {
-
-  def injectClockNode(a: Attachable)(implicit p: Parameters) = injectClockNodeFunc(a, p)
-}
-
-object GenericCrossingParams {
-  def apply(params: TileCrossingParamsLike): GenericCrossingParams = GenericCrossingParams(
-    params.crossingType,
-    params.master,
-    params.slave,
-    params.mmioBaseAddressPrefixWhere,
-    (a: Attachable, p: Parameters) => params.injectClockNode(a)(p),
-    params.forceSeparateClockReset)
-}
-
-case class GenericallyAttachableTile[TT <: BaseTile](
-    tileParams: InstantiableTileParams[TT],
-    crossingParams: GenericCrossingParams,
-    lookup: LookupByHartIdImpl) extends CanAttachTile {
-  type TileType = TT
-}
-

generators/chipyard/src/main/scala/clocking/ClockGroupDealiaser.scala

@@ -1,50 +0,0 @@
-package chipyard.clocking
-
-import chisel3._
-
-import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.prci._
-
-/**
-  * Somewhat hacky. Since not all clocks in a clock group specify a taken frequency
-  * current, this LazyModule attempts to dealias them, by finding a specified
-  * clock with a matching name.
-  *
-  * Perhaps another, simpler solution would be to pass a default.
-  *
-  */
-
-case class ClockGroupDealiaserNode()(implicit valName: ValName)
-  extends NexusNode(ClockGroupImp)(
-    dFn = { _ => ClockGroupSourceParameters() },
-    uFn = { u =>
-      require(u.size == 1)
-      val takenClocks = u.head.members.filter(_.take.nonEmpty)
-      require(takenClocks.nonEmpty,
-        "At least one sink clock in clock group must specify its take parameter")
-      u.head.copy(members = takenClocks)
-    })
-
-class ClockGroupDealiaser(name: String)(implicit p: Parameters) extends LazyModule {
-  val node = ClockGroupDealiaserNode()
-
-  lazy val module = new LazyRawModuleImp(this) {
-    require(node.out.size == 1 && node.in.size == 1,
-      "ClockGroupDealiaser requires a single ClockGroup, please use a ClockGroupAggregator")
-    val (outClocks, e @ ClockGroupEdgeParameters(_, outSinkParams,  _, _)) = node.out.head
-    val (inClocks, ClockGroupEdgeParameters(_, inSinkParams,  _, _)) = node.in.head
-    val inMap = inClocks.member.data.zip(inSinkParams.members).map({ case (b, p) => p.name -> b}).toMap
-
-    for (((outBName, outB), outName) <- outClocks.member.elements.zip(outSinkParams.members.map(_.name))) {
-      val inClock = inMap.getOrElse(outName, throw new Exception("""
-          | No clock in input group with name option matching ${outName}. At least one clock
-          | with the same must specify a frequency in its take parameter.""".stripMargin))
-      outB := inClock
-    }
-  }
-}
-
-object ClockGroupDealiaser {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupDealiaser(valName.name)).node
-}

generators/chipyard/src/main/scala/clocking/ClockNodeInjectors.scala

@@ -1,29 +0,0 @@
-
-package chipyard.clocking
-
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.prci.{ClockNode, ClockTempNode, ClockAdapterNode, ClockParameters}
-/**
-  * An adapter node hack c that just throws out the existing sink node
-  * clock parameters in favor of the provided ones.
-  */
-class ForceTakeClock(clockParams: Option[ClockParameters])(implicit p: Parameters, v: ValName) extends LazyModule {
-  val node = ClockAdapterNode(sinkFn = { s => s.copy(take = clockParams) })
-  lazy val module = new LazyRawModuleImp(this) {
-    (node.out zip node.in) map { case ((o, _), (i, _)) => o := i }
-  }
-}
-
-object ForceTakeClock {
-  def apply(clockParams: Option[ClockParameters])(implicit p: Parameters, v: ValName): ClockAdapterNode =
-    LazyModule(new ForceTakeClock(clockParams)).node
-}
-
-object ClockNodeInjectionUtils {
-  type InjectClockNodeFunc = (Attachable, Parameters) => ClockNode
-  val injectIdentityClockNode: InjectClockNodeFunc = (a: Attachable, p: Parameters) => ClockTempNode()
-  def forceTakeFrequency(freqMHz: Double): InjectClockNodeFunc =
-    (a: Attachable, p: Parameters) => ForceTakeClock(Some(ClockParameters(freqMHz)))(p, ValName("ForcedTakeClock"))
-}