Changes to tapeout transforms to support FIRRTL 1.3
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@@ -11,7 +11,7 @@ import firrtl.annotations.AnnotationYamlProtocol._
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import firrtl.passes.memlib.ReplSeqMemAnnotation
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import firrtl.transforms.BlackBoxResourceFileNameAnno
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import net.jcazevedo.moultingyaml._
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import com.typesafe.scalalogging.LazyLogging
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import logger.LazyLogging
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trait HasTapeoutOptions { self: ExecutionOptionsManager with HasFirrtlOptions =>
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var tapeoutOptions = TapeoutOptions()
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@@ -161,36 +161,27 @@ sealed trait GenerateTopAndHarnessApp extends LazyLogging { this: App =>
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// FIRRTL options
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lazy val annoFiles = firrtlOptions.annotationFileNames
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lazy val topTransforms: Seq[Transform] = {
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Seq(
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new ReParentCircuit(synTop.get),
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new RemoveUnusedModules
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)
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}
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val topTransforms = Seq(
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new ReParentCircuit,
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new RemoveUnusedModules
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)
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lazy val rootCircuitTarget = CircuitTarget(harnessTop.get)
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lazy val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++
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tapeoutOptions.topDotfOut.map(BlackBoxResourceFileNameAnno(_))
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lazy val topOptions = firrtlOptions.copy(
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customTransforms = firrtlOptions.customTransforms ++ topTransforms,
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annotations = firrtlOptions.annotations ++ tapeoutOptions.topDotfOut.map(BlackBoxResourceFileNameAnno(_))
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annotations = firrtlOptions.annotations ++ topAnnos
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)
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class AvoidExtModuleCollisions(mustLink: Seq[ExtModule]) extends Transform {
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def inputForm = HighForm
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def outputForm = HighForm
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def execute(state: CircuitState): CircuitState = {
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state.copy(circuit = state.circuit.copy(modules = state.circuit.modules ++ mustLink))
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}
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}
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private def harnessTransforms(topExtModules: Seq[ExtModule]): Seq[Transform] = {
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// XXX this is a hack, we really should be checking the masters to see if they are ExtModules
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val externals = Set(harnessTop.get, synTop.get, "SimSerial", "SimDTM")
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Seq(
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new ConvertToExtMod((m) => m.name == synTop.get),
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new RemoveUnusedModules,
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new AvoidExtModuleCollisions(topExtModules),
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new RenameModulesAndInstances((old) => if (externals contains old) old else (old + "_in" + harnessTop.get))
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)
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}
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val harnessTransforms = Seq(
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new ConvertToExtMod,
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new RemoveUnusedModules,
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new AvoidExtModuleCollisions,
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new AddSuffixToModuleNames
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)
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// Dump firrtl and annotation files
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protected def dump(res: FirrtlExecutionSuccess, firFile: Option[String], annoFile: Option[String]): Unit = {
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@@ -230,17 +221,26 @@ sealed trait GenerateTopAndHarnessApp extends LazyLogging { this: App =>
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// Execute top and get list of ExtModules to avoid collisions
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val topExtModules = executeTop()
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val externals = Seq("SimSerial", "SimDTM") ++ harnessTop ++ synTop
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val harnessAnnos =
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tapeoutOptions.harnessDotfOut.map(BlackBoxResourceFileNameAnno(_)).toSeq ++
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externals.map(ext => KeepNameAnnotation(rootCircuitTarget.module(ext))) ++
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harnessTop.map(ht => ModuleNameSuffixAnnotation(rootCircuitTarget, s"_in${ht}")) ++
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synTop.map(st => ConvertToExtModAnnotation(rootCircuitTarget.module(st))) :+
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LinkExtModulesAnnotation(topExtModules)
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// For harness run, change some firrtlOptions (below) for harness phase
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// customTransforms: setup harness transforms, add AvoidExtModuleCollisions
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// outputFileNameOverride: change to harnessOutput
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// conf file must change to harnessConf by mapping annotations
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optionsManager.firrtlOptions = firrtlOptions.copy(
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customTransforms = firrtlOptions.customTransforms ++ harnessTransforms(topExtModules),
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customTransforms = firrtlOptions.customTransforms ++ harnessTransforms,
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outputFileNameOverride = tapeoutOptions.harnessOutput.get,
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annotations = firrtlOptions.annotations.map({
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case ReplSeqMemAnnotation(i, o) => ReplSeqMemAnnotation(i, tapeoutOptions.harnessConf.get)
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case a => a
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}) ++ tapeoutOptions.harnessDotfOut.map(BlackBoxResourceFileNameAnno(_))
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}) ++ harnessAnnos
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)
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val harnessResult = firrtl.Driver.execute(optionsManager)
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harnessResult match {
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