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Changes to tapeout transforms to support FIRRTL 1.3

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This commit is contained in:
Albert Magyar
2020-05-06 21:40:23 +00:00
parent e230e8cf3f
commit acda0a3490
8 changed files with 150 additions and 94 deletions
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4
tapeout/src/main/scala/transforms/.pads/AddIOPadsTransform.scala
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@@ -39,7 +39,7 @@ class AddIOPadsTransform extends Transform with SeqTransformBased {
PadPlacementFile.generate(techLoc, targetDir, padFrameName, portPads, supplyPads)
transformList ++= Seq(
Legalize,
ResolveGenders,
ResolveFlows,
// Types really need to be known...
InferTypes,
new AddPadFrame(x.topModName, padFrameName, topInternalName, portPads, supplyPads),
@@ -48,7 +48,7 @@ class AddIOPadsTransform extends Transform with SeqTransformBased {
InferTypes,
Uniquify,
ResolveKinds,
ResolveGenders
ResolveFlows
)
// Expects BlackBox helper to be run after to inline pad Verilog!
val ret = runTransforms(state)

6
tapeout/src/main/scala/transforms/.pads/AddPadFrame.scala
View File

@@ -112,8 +112,8 @@ class AddPadFrame(
// Normal verilog in/out can be mapped to uint, sint, or clocktype, so need cast
case _ =>
val padBBType = UIntType(getWidth(p.port.tpe))
val padInRef = WSubField(padRef, DigitalPad.inName, padBBType, UNKNOWNGENDER)
val padOutRef = WSubField(padRef, DigitalPad.outName, padBBType, UNKNOWNGENDER)
val padInRef = WSubField(padRef, DigitalPad.inName, padBBType, UnknownFlow)
val padOutRef = WSubField(padRef, DigitalPad.outName, padBBType, UnknownFlow)
val (rhsPadIn, lhsPadOut) = p.portDirection match {
case Input => (extRef, intRef)
case Output => (intRef, extRef)
@@ -130,4 +130,4 @@ class AddPadFrame(
Module(NoInfo, padFrameName, ports = intPorts ++ extPorts, body = Block(ioPadInsts ++ connects ++ supplyPadInsts))
}
}
}