Move TestHarness to chipyard.harness, make chipyard/harness directory
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@@ -13,8 +13,8 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
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import sifive.blocks.devices.uart._
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import chipyard._
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import chipyard.harness.{ApplyHarnessBinders}
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import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem}
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import chipyard.harness._
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import chipyard.iobinders.{HasIOBinders}
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class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences
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