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Move TestHarness to chipyard.harness, make chipyard/harness directory

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This commit is contained in:
Jerry Zhao
2023-05-07 23:16:35 -07:00
parent 352cc773b5
commit ac281daa78
23 changed files with 38 additions and 38 deletions
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4
docs/Advanced-Concepts/Harness-Clocks.rst
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@@ -18,12 +18,12 @@ for a new clock domain.
This is useful for simulating systems in which modules in the harness have independent clock domains
from the DUT.
Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/TestHarness.scala``.
Requests for a harness clock is done by the ``HarnessClockInstantiator`` class in ``generators/chipyard/src/main/scala/harness/TestHarness.scla``.
This class is accessed in harness components by referencing the Rocket Chip parameters key ``p(HarnessClockInstantiatorKey)``.
Then you can request a clock and syncronized reset at a particular frequency by invoking the ``requestClockBundle`` function.
Take the following example:
.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala
.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala
:language: scala
:start-after: DOC include start: HarnessClockInstantiatorEx
:end-before: DOC include end: HarnessClockInstantiatorEx

2
docs/Customization/IOBinders.rst
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@@ -31,7 +31,7 @@ Like ``IOBinders``, ``HarnessBinders`` are defined using macros (``OverrideHarne
For exmaple, the ``WithUARTAdapter`` will connect the UART SW display adapter to the ports generated by the ``WithUARTIOCells`` described earlier, if those ports are present.
.. literalinclude:: ../../generators/chipyard/src/main/scala/HarnessBinders.scala
.. literalinclude:: ../../generators/chipyard/src/main/scala/harness/HarnessBinders.scala
:language: scala
:start-after: DOC include start: WithUARTAdapter
:end-before: DOC include end: WithUARTAdapter

6
docs/VLSI/ASAP7-Tutorial.rst
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@@ -115,7 +115,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped
.. code-block:: shell
./view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds
./view_gds.py build/chipyard.harness.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds
By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names.
@@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre:
.. code-block:: shell
make drc CONFIG=TinyRocketConfig
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc
./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc
make lvs CONFIG=TinyRocketConfig
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs
./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__.
Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors.

6
docs/VLSI/Sky130-Commercial-Tutorial.rst
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@@ -121,7 +121,7 @@ It is recommended that you edit these variables directly in the Makefile rather
The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources
and (2) the mapping of memory instances in the design to SRAM macros;
all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory.
all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
Note that the files in ``generated-src`` vary for each tool/technology flow.
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate
@@ -168,9 +168,9 @@ To run DRC & LVS, and view the results in Calibre:
.. code-block:: shell
make drc tutorial=sky130-commercial
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
make lvs tutorial=sky130-commercial
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.

10
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
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@@ -149,7 +149,7 @@ It is recommended that you edit these variables directly in the Makefile rather
The ``buildfile`` make target has dependencies on both (1) the Verilog that is elaborated from all Chisel sources
and (2) the mapping of memory instances in the design to SRAM macros;
all files related to these two steps reside in the ``generated-src/chipyard.TestHarness.TinyRocketConfig-ChipTop`` directory.
all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory.
Note that the files in ``generated-src`` vary for each tool/technology flow.
This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows
(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate
@@ -197,7 +197,7 @@ Hammer generates a convenient script to launch these sessions
.. code-block:: shell
cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
cd ./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir
./generated-scripts/open_chip
Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout,
@@ -212,7 +212,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin
.. code-block:: shell
cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir
cd build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/par-rundir
./generated_scripts/open_chip -h
"
Usage: ./generated-scripts/open_chip [-t] [openroad_db_name]
@@ -245,9 +245,9 @@ To run DRC & LVS in Magic & Netgen, respectively:
.. code-block:: shell
make drc tutorial=sky130-openroad
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
make lvs tutorial=sky130-openroad
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
./build/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Note that in ``sky130-openroad.yml`` we have set the following YAML keys: