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Merge pull request #215 from ucb-bar/dev-tracegen

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Add TraceGen project
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Howard Mao
2019-08-31 05:21:51 +08:00
committed by GitHub
parent d4c12f2b86 c33c6a2985
commit ab888d32a7
12 changed files with 323 additions and 15 deletions
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9
docs/Customization/Adding-An-Accelerator.rst
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@@ -61,15 +61,6 @@ the ``example`` project, change the final line in build.sbt to the following.
lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject)
Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the Chipyard top level.
This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files.
.. code-block:: shell
PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache example yourproject) \
$(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils)
MMIO Peripheral
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