From aa4a44925e2bdf95296f26b6bd9a474529785f77 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 2 Nov 2020 10:40:39 -0800 Subject: [PATCH] [clocking] Add ScalaTests for the divider-only PLL configurator --- .../clocking/SimplePllConfigurationSpec.scala | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala diff --git a/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala new file mode 100644 index 00000000..897ab0f4 --- /dev/null +++ b/generators/chipyard/src/test/scala/clocking/SimplePllConfigurationSpec.scala @@ -0,0 +1,21 @@ +//See LICENSE for license details. +package chipyard.clocking + +import freechips.rocketchip.prci._ + +class SimplePllConfigurationSpec extends org.scalatest.FlatSpec { + + def conf(freqMHz: Iterable[Double]): SimplePllConfiguration = new SimplePllConfiguration("test", + freqMHz.map({ f => ClockSinkParameters( + name = Some(s"desiredFreq_$f"), + take = Some(ClockParameters(f))) }).toSeq) + + def tryConf(freqMHz: Double*): Unit = { + val freqStr = freqMHz.mkString(", ") + it should s"configure for ${freqStr} MHz" in { conf(freqMHz) } + } + + tryConf(3200.0, 1600.0, 1000.0, 100.0) + tryConf(3200.0, 1600.0) + tryConf(3200.0, 1066.7) +}