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Fix IOCells generation

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* Fixes Bool wires matching both Reset and Bits
This commit is contained in:
Jerry Zhao
2020-06-30 12:24:05 -07:00
parent 7e6e19b8ad
commit aa1c90c4cc
1 changed files with 1 additions and 1 deletions
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2
iocell/src/main/scala/chisel/IOCell.scala
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@@ -202,7 +202,6 @@ object IOCell {
}
case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) {
@@ -248,6 +247,7 @@ object IOCell {
}
}
}
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Vec[_], padSignal: Vec[_]) => {
require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>