wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump rocket-chip + submodules for new clustered-tile API

Browse Source
This commit is contained in:
Jerry Zhao
2023-10-17 14:38:28 -07:00
parent 2b16b9bad1
commit aa057239f2
33 changed files with 116 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -8,7 +8,7 @@ import chisel3._
import chisel3.experimental.{IO, annotate}
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, HasTiles}
import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
@@ -103,8 +103,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
// FireSim ModelMultithreading
chiptops.foreach {
case c: ChipTop => c.lazySystem match {
case ls: HasTiles => {
if (p(FireSimMultiCycleRegFile)) ls.tiles.map {
case ls: InstantiatesHierarchicalElements => {
if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
@@ -120,7 +120,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
}
case _ =>
}
if (p(FireSimFAME5)) ls.tiles.map {
if (p(FireSimFAME5)) ls.totalTiles.values.map {
case b: BoomTile =>
annotate(EnableModelMultiThreadingAnnotation(b.module))
case r: RocketTile =>