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restore sim_files recipe

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Harrison Liew
2023-02-02 14:01:32 -08:00
committed by abejgonzalez
parent 48539353b0
commit a9f9f32078
1 changed files with 13 additions and 1 deletions
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14
vlsi/Makefile
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@@ -101,6 +101,18 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
######################################################################################### #########################################################################################
include $(base_dir)/vcs.mk include $(base_dir)/vcs.mk
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
@@ -117,7 +129,7 @@ $(SIM_CONF): $(sim_common_files)
echo " input_files_meta: 'append'" >> $@ echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@ echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@ echo " options:" >> $@
for x in $(VCS_NONCC_OPTS); do \ for x in $(filter-out -f $(sim_common_files),$(VCS_NONCC_OPTS)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " options_meta: 'append'" >> $@ echo " options_meta: 'append'" >> $@