From a9f632575e93979de14fedc5fa905373aa59891a Mon Sep 17 00:00:00 2001
From: Vamber Yang <vamber@a8.Millennium.Berkeley.EDU>
Date: Wed, 5 Apr 2023 23:54:03 -0700
Subject: [PATCH] Added config for GPU mem tracer

---
 fpga/fpga-shells                              |  2 +-
 .../chipyard/src/main/scala/DigitalTop.scala  |  5 ++++
 .../src/main/scala/config/GPUConfig.scala     | 24 +++++++++++++++++++
 .../src/main/scala/config/RocketConfigs.scala |  3 +++
 generators/rocket-chip                        |  2 +-
 tools/chisel-testers                          |  1 +
 6 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 generators/chipyard/src/main/scala/config/GPUConfig.scala
 create mode 160000 tools/chisel-testers

diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index b6cd1bb7..474ad191 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9
+Subproject commit 474ad19113b89ed5679695b269acdb011b9b871a
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 2777ba36..fef4a09f 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -25,6 +25,11 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
   with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
+
+
+  with freechips.rocketchip.tilelink.CanHaveGPUTracer // Enable GPU Tracer
+
+
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
diff --git a/generators/chipyard/src/main/scala/config/GPUConfig.scala b/generators/chipyard/src/main/scala/config/GPUConfig.scala
new file mode 100644
index 00000000..c4497709
--- /dev/null
+++ b/generators/chipyard/src/main/scala/config/GPUConfig.scala
@@ -0,0 +1,24 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+
+
+
+class GPUTracerConfig extends Config(
+
+  
+  // Attaching GPU Tracer to SBus
+  new freechips.rocketchip.tilelink.WithGPUTracer(4, "vecadd.core1.thread4.trace")++
+  
+
+  // Creating L2
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
+  new chipyard.config.WithSystemBusWidth(64) ++ 
+  
+  new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
+  new chipyard.config.AbstractConfig
+  )
+
+
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index e8f72bfb..c0f6ec0c 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -7,6 +7,9 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 // Rocket Configs
 // --------------
 
+
+
+
 class RocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 478fc5ac..47113c1c 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 478fc5ac52b87cfa2d459cc571df44613046b1b4
+Subproject commit 47113c1c44ea00f10964330f626a797cba34a5b8
diff --git a/tools/chisel-testers b/tools/chisel-testers
new file mode 160000
index 00000000..ce4e027e
--- /dev/null
+++ b/tools/chisel-testers
@@ -0,0 +1 @@
+Subproject commit ce4e027e5f3d871df59236b8471ea3e5be40130e