First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
This commit is contained in:
James Dunn
65
fpga/src/main/scala/arty/Config.scala
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65
fpga/src/main/scala/arty/Config.scala
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@@ -0,0 +1,65 @@
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.mockaon._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.pwm._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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// Default FreedomEConfig
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class DefaultFreedomEConfig extends Config (
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new WithNBreakpoints(2) ++
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new WithNExtTopInterrupts(0) ++
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new WithJtagDTM ++
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new TinyConfig
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)
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// Freedom E300 Arty Dev Kit Peripherals
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class E300DevKitPeripherals extends Config((site, here, up) => {
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case PeripheryGPIOKey => List(
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GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
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case PeripheryPWMKey => List(
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PWMParams(address = 0x10015000, cmpWidth = 8),
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PWMParams(address = 0x10025000, cmpWidth = 16),
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PWMParams(address = 0x10035000, cmpWidth = 16))
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case PeripherySPIKey => List(
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SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3),
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SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3))
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case PeripherySPIFlashKey => List(
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SPIFlashParams(
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fAddress = 0x20000000,
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rAddress = 0x10014000,
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defaultSampleDel = 3))
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case PeripheryUARTKey => List(
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UARTParams(address = 0x10013000),
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UARTParams(address = 0x10023000))
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case PeripheryI2CKey => List(
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I2CParams(address = 0x10016000))
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case PeripheryMockAONKey =>
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MockAONParams(address = 0x10000000)
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case PeripheryMaskROMKey => List(
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MaskROMParams(address = 0x10000, name = "BootROM"))
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})
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// Freedom E300 Arty Dev Kit Peripherals
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class E300ArtyDevKitConfig extends Config(
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new E300DevKitPeripherals ++
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new DefaultFreedomEConfig().alter((site,here,up) => {
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case DTSTimebase => BigInt(32768)
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case JtagDTMKey => new JtagDTMConfig (
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idcodeVersion = 2,
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idcodePartNum = 0x000,
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idcodeManufId = 0x489,
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debugIdleCycles = 5)
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})
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)
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193
fpga/src/main/scala/arty/FPGAChip.scala
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193
fpga/src/main/scala/arty/FPGAChip.scala
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@@ -0,0 +1,193 @@
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import Chisel._
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import chisel3.core.{attach}
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy.{LazyModule}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
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import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
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//-------------------------------------------------------------------------
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// E300ArtyDevKitFPGAChip
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//-------------------------------------------------------------------------
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class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell {
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//-----------------------------------------------------------------------
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// Clock divider
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//-----------------------------------------------------------------------
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val slow_clock = Wire(Bool())
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// Divide clock by 256, used to generate 32.768 kHz clock for AON block
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withClockAndReset(clock_8MHz, ~mmcm_locked) {
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val clockToggleReg = RegInit(false.B)
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val (_, slowTick) = Counter(true.B, 256)
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when (slowTick) {clockToggleReg := ~clockToggleReg}
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slow_clock := clockToggleReg
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}
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//-----------------------------------------------------------------------
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// DUT
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//-----------------------------------------------------------------------
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withClockAndReset(clock_32MHz, ck_rst) {
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val dut = Module(new E300ArtyDevKitPlatform)
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//---------------------------------------------------------------------
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// SPI flash IOBUFs
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//---------------------------------------------------------------------
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IOBUF(qspi_sck, dut.io.pins.qspi.sck)
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IOBUF(qspi_cs, dut.io.pins.qspi.cs(0))
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IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0))
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IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1))
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IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2))
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IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3))
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//---------------------------------------------------------------------
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// JTAG IOBUFs
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//---------------------------------------------------------------------
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dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt
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IOBUF(jd_5, dut.io.pins.jtag.TMS)
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PULLUP(jd_5)
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IOBUF(jd_4, dut.io.pins.jtag.TDI)
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PULLUP(jd_4)
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IOBUF(jd_0, dut.io.pins.jtag.TDO)
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// mimic putting a pullup on this line (part of reset vote)
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SRST_n := IOBUF(jd_6)
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PULLUP(jd_6)
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// jtag reset
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val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz)
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dut.io.jtag_reset := jtag_power_on_reset
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// debug reset
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dut_ndreset := dut.io.ndreset
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//---------------------------------------------------------------------
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// Assignment to package pins
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//---------------------------------------------------------------------
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// Pins IO0-IO13
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//
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// FTDI UART TX/RX are not connected to ck_io[0,1]
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// the way they are on Arduino boards. We copy outgoing
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// data to both places, switch 3 (sw[3]) determines whether
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// input to UART comes from FTDI chip or gpio_16 (shield pin PD0)
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val iobuf_ck0 = Module(new IOBUF())
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iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval
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iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe
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attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX
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val iobuf_uart_txd = Module(new IOBUF())
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iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval
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iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe
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attach(iobuf_uart_txd.io.IO, uart_txd_in)
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// gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3]
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val sw_3_in = IOBUF(sw_3)
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dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in,
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iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie,
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iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie)
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IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17))
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// Shield header row 0: PD2-PD7
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IOBUF(ck_io(2), dut.io.pins.gpio.pins(18))
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IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1)
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IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0)
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IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2)
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IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3)
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IOBUF(ck_io(7), dut.io.pins.gpio.pins(23))
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// Header row 1: PB0-PB5
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IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0)
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IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1)
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IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2)
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IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3)
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IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO
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IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK
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dut.io.pins.gpio.pins(6).i.ival := 0.U
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dut.io.pins.gpio.pins(7).i.ival := 0.U
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dut.io.pins.gpio.pins(8).i.ival := 0.U
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// Header row 3: A0-A5 (we don't support using them as analog inputs)
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// just treat them as regular digital GPIOs
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IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2)
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IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0)
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IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1)
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IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA
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IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL
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// Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty
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// assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active
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IOBUF(led0_r, dut.io.pins.gpio.pins(1))
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IOBUF(led0_g, dut.io.pins.gpio.pins(2))
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IOBUF(led0_b, dut.io.pins.gpio.pins(3))
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// Note that this is the one which is actually connected on the HiFive/Crazy88
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// Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active
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IOBUF(led1_r, dut.io.pins.gpio.pins(19))
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IOBUF(led1_g, dut.io.pins.gpio.pins(21))
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IOBUF(led1_b, dut.io.pins.gpio.pins(22))
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// and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active
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IOBUF(led2_r, dut.io.pins.gpio.pins(11))
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IOBUF(led2_g, dut.io.pins.gpio.pins(12))
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IOBUF(led2_b, dut.io.pins.gpio.pins(13))
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// Only 19 out of 20 shield pins connected to GPIO pins
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// Shield pin A5 (pin 14) left unconnected
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// The buttons are connected to some extra GPIO pins not connected on the
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// HiFive1 board
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IOBUF(btn_0, dut.io.pins.gpio.pins(15))
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IOBUF(btn_1, dut.io.pins.gpio.pins(30))
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IOBUF(btn_2, dut.io.pins.gpio.pins(31))
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val iobuf_btn_3 = Module(new IOBUF())
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iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval
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iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe
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attach(btn_3, iobuf_btn_3.io.IO)
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dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie
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// UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1
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IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX
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IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX
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// SPI2 pins mapped to 6 pin ICSP connector (standard on later
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// arduinos) These are connected to some extra GPIO pins not connected
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// on the HiFive1 board
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IOBUF(ck_ss, dut.io.pins.gpio.pins(26))
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IOBUF(ck_mosi, dut.io.pins.gpio.pins(27))
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IOBUF(ck_miso, dut.io.pins.gpio.pins(28))
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IOBUF(ck_sck, dut.io.pins.gpio.pins(29))
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// Use the LEDs for some more useful debugging things
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IOBUF(led_0, ck_rst)
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IOBUF(led_1, SRST_n)
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IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival)
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IOBUF(led_3, dut.io.pins.gpio.pins(14))
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//---------------------------------------------------------------------
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// Unconnected inputs
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//---------------------------------------------------------------------
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dut.io.pins.aon.erst_n.i.ival := ~reset_periph
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dut.io.pins.aon.lfextclk.i.ival := slow_clock
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dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U
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}
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}
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178
fpga/src/main/scala/arty/Platform.scala
Normal file
178
fpga/src/main/scala/arty/Platform.scala
Normal file
@@ -0,0 +1,178 @@
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.ResetCatchAndSync
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import freechips.rocketchip.system._
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import sifive.blocks.devices.mockaon._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.jtag._
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import sifive.blocks.devices.pwm._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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import sifive.blocks.devices.pinctrl._
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//-------------------------------------------------------------------------
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// PinGen
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//-------------------------------------------------------------------------
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object PinGen {
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def apply(): BasePin = {
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val pin = new BasePin()
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pin
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}
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}
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//-------------------------------------------------------------------------
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// E300ArtyDevKitPlatformIO
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//-------------------------------------------------------------------------
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class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
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val pins = new Bundle {
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val jtag = new JTAGPins(() => PinGen(), false)
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val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))
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val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))
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val aon = new MockAONWrapperPins()
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}
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val jtag_reset = Bool(INPUT)
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val ndreset = Bool(OUTPUT)
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}
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//-------------------------------------------------------------------------
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// E300ArtyDevKitPlatform
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//-------------------------------------------------------------------------
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class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
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val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
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val io = new E300ArtyDevKitPlatformIO
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// This needs to be de-asserted synchronously to the coreClk.
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val async_corerst = sys.aon.rsts.corerst
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// Add in debug-controlled reset.
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sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
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Debug.connectDebugClockAndReset(sys.debug, clock)
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//-----------------------------------------------------------------------
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// Check for unsupported rocket-chip connections
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//-----------------------------------------------------------------------
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require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
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//-----------------------------------------------------------------------
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// Build GPIO Pin Mux
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//-----------------------------------------------------------------------
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// Pin Mux for UART, SPI, PWM
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// First convert the System outputs into "IOF" using the respective *GPIOPort
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// converters.
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val sys_uart = sys.uart
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val sys_pwm = sys.pwm
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val sys_spi = sys.spi
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val sys_i2c = sys.i2c
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val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))}
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val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))}
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val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))}
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val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))}
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(uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
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(pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) }
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(spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
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(i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
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//-----------------------------------------------------------------------
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// Default Pin connections before attaching pinmux
|
||||
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for (iof_0 <- sys.gpio(0).iof_0.get) {
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iof_0.default()
|
||||
}
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||||
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||||
for (iof_1 <- sys.gpio(0).iof_1.get) {
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iof_1.default()
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}
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||||
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//-----------------------------------------------------------------------
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val iof_0 = sys.gpio(0).iof_0.get
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val iof_1 = sys.gpio(0).iof_1.get
|
||||
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||||
// SPI1 (0 is the dedicated)
|
||||
BasePinToIOF(spi_pins(0).cs(0), iof_0(2))
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BasePinToIOF(spi_pins(0).dq(0), iof_0(3))
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BasePinToIOF(spi_pins(0).dq(1), iof_0(4))
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BasePinToIOF(spi_pins(0).sck, iof_0(5))
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BasePinToIOF(spi_pins(0).dq(2), iof_0(6))
|
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BasePinToIOF(spi_pins(0).dq(3), iof_0(7))
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BasePinToIOF(spi_pins(0).cs(1), iof_0(8))
|
||||
BasePinToIOF(spi_pins(0).cs(2), iof_0(9))
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||||
BasePinToIOF(spi_pins(0).cs(3), iof_0(10))
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||||
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||||
// SPI2
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||||
BasePinToIOF(spi_pins(1).cs(0), iof_0(26))
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||||
BasePinToIOF(spi_pins(1).dq(0), iof_0(27))
|
||||
BasePinToIOF(spi_pins(1).dq(1), iof_0(28))
|
||||
BasePinToIOF(spi_pins(1).sck, iof_0(29))
|
||||
BasePinToIOF(spi_pins(1).dq(2), iof_0(30))
|
||||
BasePinToIOF(spi_pins(1).dq(3), iof_0(31))
|
||||
|
||||
// I2C
|
||||
if (p(PeripheryI2CKey).length == 1) {
|
||||
BasePinToIOF(i2c_pins(0).sda, iof_0(12))
|
||||
BasePinToIOF(i2c_pins(0).scl, iof_0(13))
|
||||
}
|
||||
|
||||
// UART0
|
||||
BasePinToIOF(uart_pins(0).rxd, iof_0(16))
|
||||
BasePinToIOF(uart_pins(0).txd, iof_0(17))
|
||||
|
||||
// UART1
|
||||
BasePinToIOF(uart_pins(1).rxd, iof_0(24))
|
||||
BasePinToIOF(uart_pins(1).txd, iof_0(25))
|
||||
|
||||
//PWM
|
||||
BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) )
|
||||
BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) )
|
||||
BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) )
|
||||
BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) )
|
||||
|
||||
BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19))
|
||||
BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20))
|
||||
BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21))
|
||||
BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22))
|
||||
|
||||
BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10))
|
||||
BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11))
|
||||
BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12))
|
||||
BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13))
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Drive actual Pads
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
// Result of Pin Mux
|
||||
GPIOPinsFromPort(io.pins.gpio, sys.gpio(0))
|
||||
|
||||
// Dedicated SPI Pads
|
||||
SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
|
||||
|
||||
// JTAG Debug Interface
|
||||
val sjtag = sys.debug.get.systemjtag.get
|
||||
JTAGPinsFromPort(io.pins.jtag, sjtag.jtag)
|
||||
sjtag.reset := io.jtag_reset
|
||||
sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
|
||||
|
||||
io.ndreset := sys.debug.get.ndreset
|
||||
|
||||
// AON Pads -- direct connection is OK because
|
||||
// EnhancedPin is hard-coded in MockAONPads
|
||||
// and thus there is no .fromPort method.
|
||||
io.pins.aon <> sys.aon.pins
|
||||
}
|
||||
51
fpga/src/main/scala/arty/System.scala
Normal file
51
fpga/src/main/scala/arty/System.scala
Normal file
@@ -0,0 +1,51 @@
|
||||
// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
|
||||
import Chisel._
|
||||
|
||||
import freechips.rocketchip.config._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.devices.debug._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.system._
|
||||
|
||||
import sifive.blocks.devices.mockaon._
|
||||
import sifive.blocks.devices.gpio._
|
||||
import sifive.blocks.devices.pwm._
|
||||
import sifive.blocks.devices.spi._
|
||||
import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.i2c._
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// E300ArtyDevKitSystem
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
|
||||
with HasPeripheryDebug
|
||||
with HasPeripheryMockAON
|
||||
with chipyard.example.CanHavePeripheryGCD
|
||||
with HasPeripheryUART
|
||||
with HasPeripherySPIFlash
|
||||
with HasPeripherySPI
|
||||
with HasPeripheryGPIO
|
||||
with HasPeripheryPWM
|
||||
with HasPeripheryI2C {
|
||||
override lazy val module = new E300ArtyDevKitSystemModule(this)
|
||||
}
|
||||
|
||||
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
|
||||
extends RocketSubsystemModuleImp(_outer)
|
||||
with HasPeripheryDebugModuleImp
|
||||
with chipyard.example.CanHavePeripheryGCDModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripherySPIModuleImp
|
||||
with HasPeripheryGPIOModuleImp
|
||||
with HasPeripherySPIFlashModuleImp
|
||||
with HasPeripheryMockAONModuleImp
|
||||
with HasPeripheryPWMModuleImp
|
||||
with HasPeripheryI2CModuleImp {
|
||||
// Reset vector is set to the location of the mask rom
|
||||
val maskROMParams = p(PeripheryMaskROMKey)
|
||||
global_reset_vector := maskROMParams(0).address.U
|
||||
}
|
||||
Reference in New Issue
Block a user