First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.

fpga/bootrom/xip/xip.S

@@ -0,0 +1,16 @@
+// See LICENSE for license details.
+// Execute in place
+// Jump directly to XIP_TARGET_ADDR
+
+  .section .text.init
+  .option norvc
+  .globl _start
+_start:
+  csrr a0, mhartid
+  la a1, dtb
+  li t0, XIP_TARGET_ADDR
+  jr t0
+
+  .section .rodata
+dtb:
+  .incbin DEVICE_TREE