First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.

fpga/bootrom/xip/Makefile

@@ -0,0 +1,45 @@
+# RISCV environment variable must be set
+
+CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
+OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
+CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
+LFLAGS=-static -nostdlib
+
+dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
+$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
+	dtc -I dts -O dtb -o $@ $<
+
+.PHONY: dtb
+dtb: $(dtb)
+
+elf := $(BUILD_DIR)/xip.elf
+$(elf): xip.S $(dtb)
+	$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
+
+.PHONY: elf
+elf: $(elf)
+
+bin := $(BUILD_DIR)/xip.bin
+$(bin): $(elf)
+	$(OBJCOPY) -O binary $< $@
+
+.PHONY: bin
+bin: $(bin)
+
+hex := $(BUILD_DIR)/xip.hex
+$(hex): $(bin)
+	od -t x4 -An -w4 -v $< > $@
+
+.PHONY: hex
+hex: $(hex)
+
+romgen := $(BUILD_DIR)/rom.v
+$(romgen): $(hex)
+	$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
+
+.PHONY: romgen
+romgen: $(romgen)
+
+.PHONY: clean
+clean::
+	rm -rf $(hex) $(elf) 

fpga/bootrom/xip/xip.S

@@ -0,0 +1,16 @@
+// See LICENSE for license details.
+// Execute in place
+// Jump directly to XIP_TARGET_ADDR
+
+  .section .text.init
+  .option norvc
+  .globl _start
+_start:
+  csrr a0, mhartid
+  la a1, dtb
+  li t0, XIP_TARGET_ADDR
+  jr t0
+
+  .section .rodata
+dtb:
+  .incbin DEVICE_TREE