First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.

build.sbt

@@ -217,3 +217,10 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip"))
     testGrouping in Test := isolateAllTests( (definedTests in Test).value ),
     testOptions in Test += Tests.Argument("-oF")
   )
+lazy val fpgaShells = (project in file("./fpga/fpga-shells"))
+  .dependsOn(rocketchip, sifive_blocks)
+  .settings(commonSettings)
+
+lazy val freedomPlatforms = (project in file("./fpga"))
+  .dependsOn(chipyard, fpgaShells)
+  .settings(commonSettings)